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My question is about SDRAM timings for clock and DataBUS. Som designer advice that clock pin has to be the shortest one. Data Bus may be longer than these because of the some problems. But clock trace is important. When I looked at Propagation delay for transmission lines it says:

v = (3x(10^8)) / SQRT(Er)

and multiply x (length of transmission line) the exact time of the signal delay i think. (by formula)

So that confused me. if my clock signal 2 or 3 inches shorter than dataBUS from the formula it seems they wont be matched. I think some kind of signal on the receiver side will be like that :

Clk : __n

Data: ___n

Do you agree with me? How I can handle this problem (I am not sure if it is a problem)

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If distances are very short i.e. no delay then clock is exactly referenced in time to the data - there should be no problem with this scenario. On the other hand, if the delay to both clk and data is 50ns then neither should this cause a problem.

Giving precedence to the clock timing-wise sounds like a recipe for disaster and should be avoided.

Maybe there are some stupidly obvious things I have missed?

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  • \$\begingroup\$ this is my reference document : freescale.com/files/32bit/doc/app_note/AN2536.pdf in figure22 it gives a priority table and effects for shortness \$\endgroup\$
    – user22165
    Apr 12, 2013 at 11:03
  • \$\begingroup\$ I can't seem to find the data sheet for the actual device - the document you have linked to is advice for sure and I too cannot understand why they appear to want to prioritize trace delay times. I still fall-back on making lines the same delay as much as possible unless, of course this chip is designed to have trace delays different but, like I say I can't find the device data sheet. \$\endgroup\$
    – Andy aka
    Apr 12, 2013 at 12:16

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