Assume I have 2 flipflops FF1 and FF2 which are driven using multiple clocks. What might be the possible violations that we would come across? I was asked this in an interview for which I answered telling the difference in skew or the clocks would cause timing violations and metastability and further explained how to solve setup/holdtime violations . But in the end interviewer said these issues come into picture only when we use a single clock with skew/delay between the clock inputs of the 2 flipflops. So I was wondering if anyone can tell me what happens when I use multiple clocks


simulate this circuit – Schematic created using CircuitLab

  • \$\begingroup\$ Wow I dint know about the schematic editor! Interesting! \$\endgroup\$ – Rancho Apr 12 '13 at 8:51
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    \$\begingroup\$ If the clocks are significantly different a kind of aliasing can occur - this applies when clk 2 is lower than clk1 \$\endgroup\$ – Andy aka Apr 12 '13 at 10:03
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    \$\begingroup\$ Did the interviewer draw them as edge or level triggered FF's? He was trying to get you to discuss how multiphase clock schemes reduce/eliminate the skew problem and enable a more robust solution vs. a single phase edge triggered scheme. \$\endgroup\$ – placeholder Apr 12 '13 at 10:29
  • \$\begingroup\$ No this was a telephonic interview and his FFs were edge triggered. Do you know of any link which describes multiple clock usage and it's problems or advantages? \$\endgroup\$ – Rancho Apr 12 '13 at 10:36
  • \$\begingroup\$ @Rancho CLK1 will be clocking data through the logic at a decent fast pace and if CLK2 is going slower than CLK1 it may "miss" vital changes in the output of the logic - almost like you are sampling a signal too slowly - you can get aliasing effects that make a mess of things. Look up aliasing \$\endgroup\$ – Andy aka Apr 12 '13 at 10:41

The interviewer was simply mistaken. You always have to think about setup/hold time violations and the resulting possibility of metastability when considering signals passing from one clock "domain" to another, regardless of whether the clocks are "nearly synchronous" or completely asynchronous.

For signals that make transitions at a rate significantly slower than either clock, you can usually use double-FF synchronizers. In other cases, you'll need to use true asynchronous FIFOs, possibly with some sort of flow control or handshake mechanism.

  • \$\begingroup\$ One may in some sense have to "think" about them, but there are many real-world situations in which the nature of at least one clock's source will guarantee that the two inputs will never be clocked anywhere near each other, so the "thinking" may not have to extend to anything beyond "These inputs are always going to switch at least 10us apart; the s/h times on the second latch are 2ns and 5ns. Since 10us is greater than 5ns, there's no problem". \$\endgroup\$ – supercat Apr 12 '13 at 15:38
  • \$\begingroup\$ @supercat: If you can say that, then you are dealing with clocks that are in the same domain, and my comments don't apply. \$\endgroup\$ – Dave Tweed Apr 12 '13 at 15:41
  • \$\begingroup\$ Perhaps I don't understand exactly what is meant by "domain"? Suppose two independent clocks at 3.00MHz and 3.14159Mhz pass into T latches whose inputs are double-synchronized with "enable" signals, and the device which controls the enable signals will disable one latch for at least 1us before enabling the other. If the outputs of those T latches were used as clocks, would they be considered to be in the same domain or different domains? \$\endgroup\$ – supercat Apr 12 '13 at 16:00
  • \$\begingroup\$ @supercat: OK, with intermittent clocks, you're not talking about synchronous design techniques at all, and you have to apply full asynchronous design rules. Obviously, in this particular situation, you can come up with some ground rules that avoid metastability, but you at least had to "think about" it in order to get there. \$\endgroup\$ – Dave Tweed Apr 12 '13 at 17:00
  • \$\begingroup\$ By different CLK domains he just meant clocks which are independent. We are used to seeing the same clk being fed to all FFs(synchronus designs) in our courses . So from what I have learnt, I could think of only meta stability and timing violations. By multiple domains, I doubt if he meant the clocks were just a bit apart. I assume something like 2&4MHz or 5&10MHz(Maynot be real world examples). I din't question back much since I dint want to show I knew nothing about multiple clocks. So I just answered what I knew! Thanks for the answers. I will; do more research on this. \$\endgroup\$ – Rancho Apr 12 '13 at 17:21

The question is confusingly asked, which might have been the whole point of it, as it mixes up some concepts from different aspects of what is know as "open loop synchronous timing". He might have been looking for you to clarify a few key concepts. Open loop in this context means that the delays/phase is uncontrolled. Here is a brief overview to point into the direction at great simplification.

1) Global clock, edge triggered. What most people think of wrt to synchronous logic. The most popular for low end logic design because the edge triggered FF gives a simple model of sequential design, secondly, edged triggered FF are common deriving from TTL,CMOS and into the standard cell libraries that replaced them and thirdly most logic design courses only cover edge triggered designs. - the draw back is that there are two constraints: The maximum delay of the logic must be less than a limit for the circuit to operate with a given cycle time. The minimum delay must be greater than a limit related to the clock skew for the circuit to operate at any clock frequency.

The minimum delay on the logic:

\$ t_{d,logic} \ge t_{skew}+t_{hold}-t_{prop,c->Q} \$

The minimum cycle constraint is:

\$ t_{cy} \ge t_{d,logic} +t_{skew}+t_{setup}+t_{prop,c->Q} \$

2) level sensitive, dual phase clocking. Is perhaps the highest volume design regime. because this is what is used in uprocessors and more complex devices. Of course there are many variants on this, here we just look at the non-over-lapped clock version. The logic is divided by the master and slave FF's and the minimum cycle time is limited only by the prop time of each logic block and the clock-> Q of the FF's. Clock slew (with in limits) does not figure into these designs and as a result they are more robust, faster and smaller. It's not clear to me why this isn't taught as often.

\$ t_{cy} \ge t_{d,logic1} +t_{d,logic1}+2t_{prop,c->Q} \$

This second case when there is no OL clocks, and there is no second logic block reverts to the first case.

3)Pipeline timing: which we'll not discuss here.


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