Adjusting the rise and fall time of a gate driver

Question

I have a hard time understanding the specifications of the UCC27511A-Q1 gate driver.

I understand that for a period of 0.5 μs (2 MHz) it can supply a source current of 4 A and a sink current of 8 A.

The internal resistance specified is:

In my particular project I need Vgs = 12 V to activate the FET and I want to adjust the rise and fall time of the switching, and there is the problem that I do not understand.

In the datasheet, does the CLoad emulate the parasitic capacitance that is usually found in FET datasheets as Q gate charge?

If so, if my understanding is correct for 0.5 μs I have 4 A that results in 2 μC.

I calculated the power needed for Cload as specified in the datasheet, but I have a hard time understanding how to adjust my resistances for custom rise and fall times.

I would really appreciate an example.

Answer 1

In the datasheet, does the CLoad emulate the parasitic capacitance that is usually found in FET datasheet as Q gate charge?

It doesn't "emulate" it, it is the gate capacitance for a "typical" application.

So, one way to prolong the rise- and fall-time is to add capacitance in parallel with the gate - but this will waste energy proportional to the added capacitance, and thus is not desirable.

Instead, using a series current limiter will keep the energy loss fixed independently of the rise/fall time.

I haven't tried it on the breadboard, but I'd start with current sources in series with the gate driver. Something like the below may be a starting point. R1 and R3 adjust the rise- and fall-time: the larger the resistance, the slower the corresponding slew rate.

Rs1, D5, D6 and Cg1 are a reference circuit used to compare the performance of the current sources to a short circuit.

Rs1 and Rs2 model the source impedance of the gate driver.

^{simulate this circuit – Schematic created using CircuitLab}

D1 and D2 steer the high and low levels to separate current sources. This makes both transition times individually adjustable.

Q2+Q22 and Q4+Q44 are the current limiters and steer base current away from the pass elements Q1/Q3. D3 and D4 are anti-saturation diodes, and may not be needed in the physical circuit.

The voltage across the reference gate capacitor Cg1, and the slew-rate-limited gate capacitor Cg2, is shown on the plot below.

It is also possible to have just one current source inside a rectifier bridge - that way both the rising and falling edge would be controlled exactly the same:

^{simulate this circuit}

The rising- and falling edge are now controlled by the same current source and are symmetric:

At this point we may as well make our own gate driver :)

The input is driven from a 3.3V logic level source V1. Q3-Q4 are a push-pull driver stage that generates the 12V-level control voltage. Q1-Q2 are the common-base stage that controls Q3-Q4. 1V6 is a 1.6V reference level that biases the common-base input stage. D1 and D2 are Baker clamps that prevent Q3 and Q4 from saturating.

Q5-Q7-Q9 and Q6-Q8-Q10 are a pair of voltage-controlled current sources that can drive current into the gate capacitance Cg, or out of it. Vc1 is the voltage that controls the current.

D3 and D4 prevent the current source outputs from saturating by robbing the drive current when the output voltage gets close to the rails.

The rise- and fall-times are controlled by the 50Ω potentiometers Rr and Rf, respectively.

^{simulate this circuit}

The input, high-level control, and gate voltage waveforms are shown below.

Tweaking the coupling networks a bit, we get:

^{simulate this circuit}

Simulation at 1ns time step looks quite reasonable. I've tried it out on the breadboard and soldered point-to-point on a copper-clad laminate acting as a ground plane, and the simulated performance is representative of what's possible with careful construction and tweaking to match the parasitics.

If the digital PWM source doesn't have a "high drive" option in the GPIO configuration, a buffer is necessary, e.g. several paralleled 74HC04, etc.

Answer 2

Most gate drivers including the one you are asking about should be considered as a voltage source rather than a current source. If you look at the output stage of the driver you can see that the output to the gate is either connected to GND or VDD using transistors inside the driver IC:

This particular driver is a bit special because it has two pull-up transistors. The NFET is just briefly turned on during the switching time to decrease the pull-up resistance to approximately 1 Ohm. The rest of the high period the PFET is kept on and the NFET is turned off. For rise time calculation you can consider the driver as a simple 1 Ohm pull-up resistor. But you will have to limit the current to the specified 4 A. Otherwise the driver might get damaged, have a look at the absolute maximum ratings.

So to calculate or simulate rise time you could simplify the driver like this:

You need to estimate the series inductance which includes PCB layout as well as the input capacitance of the MOSFET. You end up with an RLC series circuit for which you can increase the resistance to increase rise time. The series inductance is probably in the order of some nH to tens of nH given reasonable PCB layout.