I have built a simple 8-bit processor with 16-bit address lines and 8-bit data lines; not the most efficient CPU architecture, but it does the job. As you might have guessed, this CPU is really simple: it can only fetch, decode and execute one instruction at a time.

From this follows that every piece of hardware, RAM, ROM, and so on, are really only ever accessed sequentially, meaning that at a give instant of time there is only one hardware device enabled to read/write data from/to.

Suppose I just duplicate the CPU and run it with the same clock of the first CPU, suppose also these two CPUs are somehow coordinated to run in parallel and fetch their own instructions to execute. Here comes the real electronics dilemma: if the two CPUs are in fact sharing the same RAM hardware, the same ROM hardware, and the same hardware devices, will the BUS eventually go in conflict when CPU 1 puts data onto the bus at the same time CPU 2 does?

I would like really simple answers that do not include many complicated words to address this issue, and some simple explanation on how in modern CPUs this is solved.

  • \$\begingroup\$ If you drive the two CPUs from different clocking systems with the same nameplate frequency, then they will not be running at the same rate. Close. But not exact. If you drive both CPUs from the same external clocking device (separate 'can' designed for the purpose) then their bus cycles will be in-synch but possibly slightly out of phase with each other and possibly where that phase varies a little from cycle to cycle. And yes, if they share an address/data bus and control lines competing for the same memory resources, there will likely be much troubles without extra logic and effort. \$\endgroup\$ Feb 12 at 19:17
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    \$\begingroup\$ I'm afraid you're just going to end up with complicated words and phrases. Terms like "bus contention" and "bus arbitration" are industry standard, and you'd be short-changed if we explained it only in terms that couldn't be searched on. \$\endgroup\$
    – TimWescott
    Feb 12 at 19:27
  • \$\begingroup\$ I totally agree with that. So, tell me if I'm at least right on this: No matter the design, whether we have two, four, eight, n^2 cores, the internal circuitry will be constructed such that the BUS will ever be accessesed only by one of these cores until they complete the read or write operation, passing control to the waiting cpu for the bus use. Correct me if I'm wrong. \$\endgroup\$
    – gmmk
    Feb 12 at 19:33
  • \$\begingroup\$ They don't have to share their busses if they have another, fast enough communication channel - NUMA processors do that. \$\endgroup\$
    – Lior Bilia
    Feb 12 at 19:38
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    \$\begingroup\$ What you mean to say is that instead of one BUS you can have more busses attached to as many cores as we have? Is that what defines a channel? Sorry for the ignorance, I really need to understand this. \$\endgroup\$
    – gmmk
    Feb 12 at 19:40

1 Answer 1


The problem you're describing is called "bus contention". I'm not going to pretend to be able to list all the possible solutions here, but two examples are bus arbitration and dual-port memories.

A dual-port memory is conceptually easiest: it's just one set of memory cells with two independent sets of address lines and data lines, and enough circuitry in between that the memory can be simultaneously accessed. There's a lot of different ways this can be done, but it's pretty common to lay down a requirement that the processors are running on a common clock in such a way that memory accesses to the same cell are in some way simultaneous.

Even dual-port memory can have contention, if both processors decide to write to one cell at the same time. The best way to deal with this is to design the system so that either your dual-port memory has a read-write side and a read-only side, or design it (in software or hardware) so that each processor has segments of memory that it "owns" for writing.

Bus arbitration can be done with ordinary memory. In this case you have logic with bus request and bus grant lines to each processor. Each processor must be able to activate a bus request and then wait on the bus grant coming back. The bus arbitration gets a bus requests, decides if the bus is free for that processor and then grants it. If the bus is busy and a new processor asks, it doesn't get the bus. If multiple processors ask, then the bus arbitration logic has some method of determining which processor gets the bus, and once it has, it grants the bus to the correct processor.

  • \$\begingroup\$ You can search on "bus contention" to get way more information than I've given you here. If you have a collection of sufficiently advanced books on computing system design, entire chapters will be devoted to this, and academic careers have been founded on and flourished by investigating the best ways to address the problem. \$\endgroup\$
    – TimWescott
    Feb 12 at 19:41
  • \$\begingroup\$ Yes, well I guess that at least I had a good intuition for the issue of having multiple cores in the system. Thanks, I'll have to read a couple of computing system design books to improve my little machine to support multicores. You just got an upvote. \$\endgroup\$
    – gmmk
    Feb 12 at 19:53
  • \$\begingroup\$ You can start by what's on the internet, save the books for later if you're still interested. If you've got a long-lasting enough interest in it and you're in a position to get a college degree, there's lots of programs in electrical engineering that teach this stuff. \$\endgroup\$
    – TimWescott
    Feb 12 at 20:04
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    \$\begingroup\$ @gmmk: Please note that arbitration takes place for any bus with multiple "bus masters"... even if only one of them is a CPU. Storage controllers, network controllers, high performance graphics cards will often perform DMA (direct memory access) which frees up the CPU to do other things while the bus is executing the DMA transfer. (Assumes that the CPU has some memory, such as L1 and L2 cache, that it can access directly in order to continue doing useful work without going through the bus) \$\endgroup\$
    – Ben Voigt
    Feb 13 at 4:04

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