I have built a simple 8-bit processor with 16-bit address lines and 8-bit data lines; not the most efficient CPU architecture, but it does the job. As you might have guessed, this CPU is really simple: it can only fetch, decode and execute one instruction at a time.
From this follows that every piece of hardware, RAM, ROM, and so on, are really only ever accessed sequentially, meaning that at a give instant of time there is only one hardware device enabled to read/write data from/to.
Suppose I just duplicate the CPU and run it with the same clock of the first CPU, suppose also these two CPUs are somehow coordinated to run in parallel and fetch their own instructions to execute. Here comes the real electronics dilemma: if the two CPUs are in fact sharing the same RAM hardware, the same ROM hardware, and the same hardware devices, will the BUS eventually go in conflict when CPU 1 puts data onto the bus at the same time CPU 2 does?
I would like really simple answers that do not include many complicated words to address this issue, and some simple explanation on how in modern CPUs this is solved.