Multicore CPU design dilemma on reading from/writing to hardware devices

Question

I have built a simple 8-bit processor with 16-bit address lines and 8-bit data lines; not the most efficient CPU architecture, but it does the job. As you might have guessed, this CPU is really simple: it can only fetch, decode and execute one instruction at a time.

From this follows that every piece of hardware, RAM, ROM, and so on, are really only ever accessed sequentially, meaning that at a give instant of time there is only one hardware device enabled to read/write data from/to.

Suppose I just duplicate the CPU and run it with the same clock of the first CPU, suppose also these two CPUs are somehow coordinated to run in parallel and fetch their own instructions to execute. Here comes the real electronics dilemma: if the two CPUs are in fact sharing the same RAM hardware, the same ROM hardware, and the same hardware devices, will the BUS eventually go in conflict when CPU 1 puts data onto the bus at the same time CPU 2 does?

I would like really simple answers that do not include many complicated words to address this issue, and some simple explanation on how in modern CPUs this is solved.

Answer 1

The problem you're describing is called "bus contention". I'm not going to pretend to be able to list all the possible solutions here, but two examples are bus arbitration and dual-port memories.

A dual-port memory is conceptually easiest: it's just one set of memory cells with two independent sets of address lines and data lines, and enough circuitry in between that the memory can be simultaneously accessed. There's a lot of different ways this can be done, but it's pretty common to lay down a requirement that the processors are running on a common clock in such a way that memory accesses to the same cell are in some way simultaneous.

Even dual-port memory can have contention, if both processors decide to write to one cell at the same time. The best way to deal with this is to design the system so that either your dual-port memory has a read-write side and a read-only side, or design it (in software or hardware) so that each processor has segments of memory that it "owns" for writing.

Bus arbitration can be done with ordinary memory. In this case you have logic with bus request and bus grant lines to each processor. Each processor must be able to activate a bus request and then wait on the bus grant coming back. The bus arbitration gets a bus requests, decides if the bus is free for that processor and then grants it. If the bus is busy and a new processor asks, it doesn't get the bus. If multiple processors ask, then the bus arbitration logic has some method of determining which processor gets the bus, and once it has, it grants the bus to the correct processor.