They're actually back-to-back P-channel MOSFETs. On the left, the Q1A pMOS is connected "backwards" in what is called an "ideal diode" configuration. As it's behaving like a diode, it blocks current flow if the power supply is connected in reverse.
Under normal operation, the body diode in the pMOS conducts from the drain to the source. There's an immediate voltage drop of around 1 V, but then provided the Q5-1 nMOS is conducting, R27 will pull G1 below S1, turning on the pMOS's conductive channel and reducing its resistance to a few tens of milliohms. Very little power is lost.
However, if voltage is connected backwards, the body diode in Q5-1 conducts, holding G1 and S1 at the same voltage, closing the Q1A conductive channel. S1 is also higher than D1, so the Q1A body diode blocks. No current can flow, and the circuit is isolated from the reverse voltage.
Q1B appears to do something similar to block a voltage connected at
V_ext from being fed back up the USB line. If
V_ext has a voltage connected, Q5-2 will conduct, pulling down the gate of Q5-1 via R26. If Q5-1 is off, Q1A and Q1B are both turned off. However, the body diode of Q1A will still conduct, so Q1B is needed to actually close the channel. Under USB-powered operation, Q1B is on at the same minimal resistance as Q1A, so again very little power is lost. Specifically, this configuration prioritizes
V_ext: if there's power at
V_ext, the USB power is cut off.
Q2A performs the same reverse-polarity function, but protecting
V_ext instead. It also prevents power from 'back-feeding' up
V_ext from the USB power line, as Q5-2 is off, holding Q2A's source and gate at the same voltage through R28. However, I'm not exactly clear what Q2B is doing here: when
V_ext has voltage, it conducts; when only USB voltage is present, it conducts through its body diode.
Finally, bang in a couple of power filter capacitors and you've got your design as pictured above.