I recently overcame an issue while writing some startup assembly for the STM32G474, which had to do with each peripheral having a "clock enable" bit that needs enabled before the peripheral can be used. In the course of this I observed some interesting behavior that I'd like to understand a bit better, mostly for the sake of diagnosing similar problems in the future more quickly.
If one attempts to read GPIOA_MODER at address 0x4800 0000, they will see the reset value of that register, 0xABFFFFFF. However, reading any other register from that peripheral, that is any word-aligned address between 0x4800 0000 and 0x4800 03FF, will return the exact same value. The datasheet shows GPIOA as being connected via bus "AHB2", which is itself connected through another AHB to the core.
Edit: This behavior is the same for all peripherals, reading anything inside a peripheral whose clock is off returns the reset value of its first (offset 0) register.
My intuition is that there is some address register, presumably 10 bits wide, between the core and GPIOA that is reset to zero on startup. But why then would reading from MODER give any meaningful result at all? I sort of expected that it would give zero or FFFFFFFF, cause a data abort, or, in a nicer world, return some warning value like 0xDEADC10C.
I usually use a read of a "well known" register like this to ensure that a device is working correctly, so this really threw me off for quite a while. Can someone explain what sort of chip design choices would result in this kind of observed behavior?