2
\$\begingroup\$

I would like to make a simple 2-layer board where I have 4 pairs of 100 Ohm differential pairs to be used for the LVDS signals.

According to the article https://resources.altium.com/p/routing-requirements-usb-20-2-layer-pcb this should not be a problem when using coplanar microstrip differential pairs (the example in the article is for 90 Ohm USB traces).

Image from Altium site

Changing the parameters for 100 Ohm is just setting a different value in Altium's input field, but there is absolutely no information about the required width of the GND traces outside of the differential pairs. As I have 4 differntial pairs there might be some crosstalk between the pairs when the GND traces between the pairs are too small.

Can you give me some hints about the minimum GND trace width for this confirguration?

\$\endgroup\$
1
  • \$\begingroup\$ Why do you think you need GND traces between the differential pairs? Microstrip diff pairs couple to each other, and other signals, very weakly in the plane of the signals. That is through their edges. \$\endgroup\$
    – SteveSh
    Feb 14, 2023 at 0:47

2 Answers 2

1
\$\begingroup\$

I've added a label (EG) to what I think you are asking about, which would effectively be the "external gap" between differential pairs:

Differential-coplanar diagram with external gap markup

The short answer is: make the external gap 5 times as wide as the trace width of one of the traces in the differential pair. (In other words, 5 times Wn.)

(The difference between W1 and W2 is based on etch factor. Consult your PCB fabricator to get more specifics. If they're different, use W1.)

For more information, there is another Altium article by Zachariah Peterson titled "Differential Crosstalk and Spacing Between Differential Pairs" you may be interested in.

\$\endgroup\$
1
  • \$\begingroup\$ I would use a slightly different criteria, EG >= h (substrate height). Vias can be placed freely outside of the same bound, as well; really, they can probably be placed right up by the near edge of the top ground with little effect, considering the gross manufacturing tolerance of the PCB itself compared to these much more subtle features. (And in practice, EG >= h will be very similar to EG >= 5*Wn, so this distinction isn't huge or anything.) \$\endgroup\$ Feb 14, 2023 at 2:40
0
\$\begingroup\$

That Altium example is terrible, it ignores or disregards the height above reference plane which is the primary constraint.

Rule of thumb is gap of diff-pairs to co-planar copper is between 3 to 5x dielectric height, more is better & co-planar GND is best.

\$\endgroup\$
3
  • \$\begingroup\$ Altium's diagram doesn't show the dielectric height in the diagram, but these profiles are created in the layer stack-up editor, so it is utilized despite being omitted from the graphic. It is my thought that "differential-coplanar" doesn't use the dielectric height because it is using same-layer ground as its reference. Or, perhaps better to say that dielectric height still matters, but is no longer the primary contributor. \$\endgroup\$
    – JYelton
    Feb 13, 2023 at 22:55
  • \$\begingroup\$ But both pictures/diagrams posted by OP clearly show reference plane copper layer. \$\endgroup\$
    – Kakapo
    Feb 19, 2023 at 2:39
  • \$\begingroup\$ My point was to add the clarification that since controlled impedance profiles are created in the stackup editor, the user inputs the dielectric thickness adjacent to this diagram, and therefore the software "knows" this value and uses it in its calculations, despite not showing the height dimension callout in the diagram. \$\endgroup\$
    – JYelton
    Feb 21, 2023 at 17:18

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.