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I'm building an AMD FP7r2 based platform and I have a USB Type-C port to which I want to connect USB 4.0 signals.

The USB4.0 signals can be also used for DisplayPort (the APU supports this switch), and I want to use both functions.

Here are the signals that arrive to the USB Type-C port:

USBC1_RXBP, USBC1_RXBN, USBC1_TXBP, USBC1_TXBN

USBC1_TXAN, USBC1_TXAP, USBC1_RXAN, USBC1_RXAP

USBC1_DP3_SBU1, USBC1_DP3_SBU2, USBC1_CC2_CCG6, USBC1_CC1_CCG6

My question, in order to have a port that supports USB 4.0 and DisplayPort, do I need to use USB-PD Controller? How does the CPU know if we have DisplayPort or USB4 NVMe connected to the port?

As I checked, the CC signals play a role in detecting the type of the sink.

My follow-up question, in case we connect DisplayPort, should we expect from the CPU to configure USBC1_DP3_SBU1 as DP_AUX signals?

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in order to have a port that supports USB 4.0 and DisplayPort, do I need to use USB-PD Controller? How does the CPU know if we have DisplayPort or USB4 NVMe connected to the port?

Yes, you must have a USB-PD controller in the CC path. Usually it is an off-CPU IC.

Establishing a USB4 connection is quite a bit complicated. In simplified terms, the process is as follows.

First, any external device will use a cable, and modern cables are pretty complicated things. They may be passive cables, and there are several sorts of "active" cables, having re-drivers or re-timers, supporting Thunderbolt function or not. The cables might have restrictions on physical signal speeds due to their length or material quality of wires. All this information is encoded in cable's e-Marker chips. So a cable might require some configuration over side-band channel.

When a cable is connected, the CC DC-level combination will determine the plug orientation and port role, host or device. Then the host port PD will inquire about cable properties via requests using so-called SOP' and SOP" type VDF (vendor-defined) messages.

Then the host port PD will talk to the actual "link partner" and determine its functionality (like what kind of DP it supports etc.) via plain SOP messages. Somewhere between these the PD controller will negotiate the power-delivery options, which might include "power-swap" function.

All these findings are communicated to host CPU/APU via a separate communication channel, typically over I2C protocol. This is the way how CPU/APU "knows" what it is dealing with, and turns/configures its internal MUXes into proper mode, including SB signals.

After that the host port would issue an "ENTER_MODE" message, summarizing/communicating these findings to the "link partner". An only then the USB super-speed link training begins, and actual functional communication follows.

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