I am designing a phase lock circuit using an Analog Devices ADF4107 PLL Frequency synthesizer (https://www.analog.com/en/products/adf4107.html).
The PLL is programmed manually and one of the settings is "Charge Pump Output" which can be either "normal" or "three-state".
**CP Three-State: ** This bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled.
I am trying to get a grip on the meaning of "three-stating" a charge pump (the data uses it as a verb - "when the chip is disabled, the the charge pump is three-stated").
I am guessing that this refers to the tri-state phase frequency detector, but I am very confused about the usage throughout this datasheet. If three-state is set to False (i.e. normal operation, then what is the charge pump doing?
Furthermore It seems that "three-stating" occurs upon shutdown:
When a power-down is activated the following events occur:
- All active dc current paths are removed.
- The charge pump is forced into three-state mode.
What could "three-state" vs. "normal" charge pump operation mean in this context? Which should be used for normal operation of finding and maintaining phase lock?