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I am designing a phase lock circuit using an Analog Devices ADF4107 PLL Frequency synthesizer (https://www.analog.com/en/products/adf4107.html).

The PLL is programmed manually and one of the settings is "Charge Pump Output" which can be either "normal" or "three-state".

**CP Three-State: ** This bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled.

I am trying to get a grip on the meaning of "three-stating" a charge pump (the data uses it as a verb - "when the chip is disabled, the the charge pump is three-stated").

I am guessing that this refers to the tri-state phase frequency detector, but I am very confused about the usage throughout this datasheet. If three-state is set to False (i.e. normal operation, then what is the charge pump doing?

Furthermore It seems that "three-stating" occurs upon shutdown:

When a power-down is activated the following events occur:

  • All active dc current paths are removed.
  • The charge pump is forced into three-state mode.
  • ...

What could "three-state" vs. "normal" charge pump operation mean in this context? Which should be used for normal operation of finding and maintaining phase lock?

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4 Answers 4

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If three-state is set to False (i.e. normal operation, then what is the charge pump doing?

In normal mode the CP output will pulse high or pulse low depending on the state of the phase detected. In between pulsing (idling) it will be open circuit (or the so-called third state): -

enter image description here

And, it appears that you can change normal mode (positive current, negative current and zero current) into an open circuit with just a bit of leakage current.

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The more common word is "tristate" (as an adjective or verb), not "three-state". In context, it means to make a pin high-impedance, neither driving high nor low — see "Tristate a pin".

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"three-state" is likely a translation error, and should be "tri-state".

This is another way of saying setting the output to a high-impedance state - i.e. not driving any current.

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An IC output will usually have a high output, and a low output. Some ICs allow the output to be set into a high impedance 'third state'.

Setting the output to high impedance is therefore often called 'three-stating' it.

This can be used to allow another device to take control of this pin.

In the case of your PLL IC, it has nothing to do with how many states the phase detector itself has.

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    \$\begingroup\$ "is therefore often called 'three-stating' it". On the contrary, it's rarely called 'three-stating' it, pretty much never. \$\endgroup\$
    – TonyM
    Feb 15 at 20:26
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    \$\begingroup\$ I've seen "high-Z" commonly, with "tri-state capable" meaning that the outputs can be set to high-impedance with an "output enable" signal or something like that. \$\endgroup\$
    – vir
    Feb 15 at 20:30
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    \$\begingroup\$ I've see the term "three-state" used plenty of times. \$\endgroup\$
    – Andy aka
    Feb 15 at 20:40
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    \$\begingroup\$ @TonyM: It certainly does exist and people do use it, even if it's less common than "tri-stating". \$\endgroup\$
    – psmears
    Feb 16 at 14:25
  • \$\begingroup\$ @psmears, sure, I've certainly heard 'three-state' used - but never 'three-stating'. Answer says 'often' but I've never heard it in a lot of decades with a lot of engineers and docs. Maybe it's a regional/national thing...but I'd say you could go through a lot of datasheets/appnotes/etc and not find it. I'd have skipped 'sometimes' or 'occasionally' without comment but I'd stand by that it's not 'often'. (The comment chain now makes it look a bigger deal than it's worth.) \$\endgroup\$
    – TonyM
    Feb 16 at 17:53

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