# Precision current source and mΩ measurements

I'm trying to measure some resistors in the 3-5 mΩ range. I want to use a precision current source (picture below) and an AD7791 ADC for that purpose. I also want to use a 1.2 V reference voltage (AD1580) as both a current source and the ADCs reference.

I wonder is it a good idea to feed voltage across the shunt resistor (R6) as a reference for the ADC. The reference input of the AD7791 is unbuffered and the input impedance of each reference input is dynamic. Is it necessary to buffer the AD1580 or R6 voltage with another op-amp to use it as a reference for this ADC?

• I don't mean to change the subject and I recognize your question is entirely different and only related to this circuit. But I'm just curious, anyway. Given your set-current (1.25 V / 10 Ohm) of 125 mA, have you also considered an IC like the LT3092? (If you use 0.1% resistors with it, you also won't much impact it's initial accuracy spec of 1%. You can easily use it with kelvin leads for pretty good results.) Commented Feb 15, 2023 at 22:52
• The circuit follows the one from TI AN-31. Note that nowadays you can replace the JFET + BJT with a single logic-level MOSFET. Same accuracy, better availability and less parts. Note also that OP1177 does not have rail-to-rail I/O, and the 1.25V reference voltage is below the specified common mode voltage range when used with single-sided supply.
– jpa
Commented Feb 16, 2023 at 8:01

According to the ADC datasheet, reference input current is of the order of 1μA, which if diverted away from your shunt R6 (carrying about 100mA) would represent about $$\\frac{1\mu A}{100mA}=0.001\%\$$ deviation of voltage across that resistor.

That's 10ppm, and the question is can you tolerate that? Given the errors introduced by everything else in the circuit, I imagine you can.

Of greater concern, if I've understood the current source correctly, is that the voltage at the gate of your JFET will need to be very close to zero. Closer, I believe, than this model of op-amp can achieve, without a negative supply.

• Indeed, a small MOSFET like BSS138, or using a power MOSFET in the first place e.g. IRLZ44, would be adequate substitutes here. Commented Feb 16, 2023 at 3:18
• "Of greater concern, if I've understood the current source correctly, is that the voltage at the gate of your JFET will need to be very close to zero. Closer, I believe, than this model of op-amp can achieve, without a negative supply." If I'm not mistaken this voltage depends on a j-fet model that is used. In simulation op amp output is at 2V, well above minimal 0.9V for that amplifire. Commented Feb 16, 2023 at 3:55
• @Tolik4 2V surprises me. Ve + Vbe - Vgs = 1.3 + 0.7 - 1.0 = 1V. Did I get that wrong? Commented Feb 16, 2023 at 4:26
• I'm not sure, but can assume that -1V is Vgs for zero current, and current through the j-fet in the circuit is about 2mA. Commented Feb 16, 2023 at 4:38

As shown, probably fine.

That has the advantage of compensating U4's input offset (which is small at max. 60 µV, but maybe less is desired -- a chopper/autozero type could also be used here for even less offset).

Some considerations, though:

• Noise on the DUT terminals is coupled directly into the ADC reference (via transistor capacitance). Some filtering might be desirable, but then you have some impedance or resistance between Ref and the ADC.

• Ref is only available while a load is connected, and is only in tolerance when a sufficiently low resistance load is connected, such that the pass transistor leaves saturation.

• If you ever want to change to an adjustable/programmable current source (such as a DAC into the op-amp +IN), the shunt resistor voltage will vary accordingly.

• Be sure to connect both reference and sense with appropriate Kelvin connections: V2 negative must connect to R6 bottom.

• It violates the general principle (I say "principle", but it's more of a hand-wave, or even just a feeling of consistency) of mixing the rough, high power elements with the low-power (signal level), sensitive, precision, pristine elements. As a "feeling", it's like the traditional meaning of "profane" vs. "sacred", the separation between such spaces.

I don't expect this last one to be taken very seriously, but I thought it might be interesting, as kind of a bit of flavor one may get on the art of electronics.

Basically, the feeling of the last one, is realized by the first couple concerns.

Another option is to use a multi-channel ADC and read R6 separately, and adjust the measurement in software ("self calibrating", of a sort). Most readings will be as expected (i.e. ~full scale), but this provides opportunity for a sanity check, if that should prove helpful. Maybe additional channels could prove useful elsewhere too (in an integrated system). Or maybe not; just an option.

Note the same concerns apply to the ADC inputs themselves, which are pushed right to the supply rails here (if the DUT goes open) -- their maximum range. Input common mode range is specified as rail-to-rail, so this is acceptable by itself, but leaves no margin. If these DUT terminals will be exposed to the outside world, ESD protection and filtering will be very welcome additions. (The ADC being S-D type, already rejects quite a lot of AC noise; filtering to avoid aliasing -- interference in the ~MHz range -- is all that's required.)

Finally, a caution about the current source itself: there is compensation in the circuit (good!), just mind that some output compensation may also be desirable, such as an R+C across the output terminals (typical values might be 10 nF + 10 Ω). As an amplifier, this circuit is sensitive to its load conditions, and it can happen that, between device capacitances, and op-amp compensation, it oscillates, particularly with inductive or resonant loads. So just check a few load conditions (say 0.1 to 100 µH plus any resistance within the rated range) and adjust the RC values to keep it clean.

• "Note the same concerns apply to the ADC inputs themselves, which are pushed right to the supply rails here -- their maximum range (input common mode range is specified as rail-to-rail)." Actually, as shown on picture above, ADC's AIN+ is at Vcc-Vref due to voltage drop on R1, which was added specifically for this purpose. Commented Feb 16, 2023 at 4:16
• @Tolik4 Good point. (If the DUT is disconnected, Vcc will still be applied, but I'm guessing the reading won't be very important in that case, heh.) Commented Feb 16, 2023 at 4:19

simulate this circuit – Schematic created using CircuitLab

You could use a ratiometric approach like the simple circuit above. The voltage on the sample (R3) is added to vref, which is a nominal 2.5V, which is used as the ADC reference. This reference voltage will only be affected by less than 1% over a range of 0 to 100 milliohms, and the resistance will be 0.1 * vres / vref or 0.01. You can even compensate for the voltage on the sample by subtracting it from vref. The value depends only on the accuracy of R2, R4, and R5, and not on the supply voltage V1.

Really it is a clever trick to use the voltage drop across R6 as a reference voltage because the resistance is too low. Strictly speaking, it has to be buffered because the ADC input current will be added to the 125 mA main current. But it depends on the magnitude of the input current...