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I am working on a project for LED control with MCU and LED drivers. I have an input voltage of 24 V and a DCDC converter to 3.3 V for the MCU. Each LED controller will have an output current of 1 A.

I searched all over the Internet and could not find a definite answer to the clearances rules, or the width of the trace, etc.

What are good rules to start with and so I can learn how to find specific values for these rules?

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    \$\begingroup\$ this is far too broad; you'll want to read a book, not hope that someone copies a book on circuit design and board layout into the answers to a comment here. \$\endgroup\$
    – Marcus Müller
    Commented Feb 16, 2023 at 10:14
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    \$\begingroup\$ Awesome! So you're far more ahead of the curve than I thought! If you've designed circuits, that means you understand why you do things like place capacitors close to devices, and where what current flows. Now, you know why you want traces to have a some clearance – isolation. There's a buttload of calculators out there for clearance needs to be safe against creepage. In short, at 24V and below, you won't have a problem. Same for trace widths: you know why you need wide traces, resistance/voltage drop; there's a buttload of calculators for that out there, too. Generally, a trace that's \$\endgroup\$
    – Marcus Müller
    Commented Feb 16, 2023 at 10:20
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    \$\begingroup\$ too wide doesn't hurt much (aside from making layout more complicated, potentially, if things start to get crammed). You design your traces to be wide enough so that the voltage drop doesn't matter to your use case. As the circuit designer, you're the only one who knows what that means – a 0.2Ω trace in series with a 10 kΩ resistor doesn't matter much, but in series with a 0.1Ω current sensing shunt, it does. That's basically all there is to it (at least for non-RF circuits). \$\endgroup\$
    – Marcus Müller
    Commented Feb 16, 2023 at 10:20
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    \$\begingroup\$ IPC-2221 is a standard for all things PCB. You can d/l the "a" version I believe. Tables of creepage and clearance are contained. \$\endgroup\$
    – Andy aka
    Commented Feb 16, 2023 at 10:24
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    \$\begingroup\$ It's possible that your PCB manufacturer will have a set of suggested design rules. \$\endgroup\$
    – pjc50
    Commented Feb 16, 2023 at 10:25

3 Answers 3

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The below image is table 6-1 from the IPC-2221 standards. These are the minimum conductor spacings as a function of the voltage between two conductors, for various scenarios:

IPC-221 table 6-1

In my experience, these values work fine for "device in typical environment." Due consideration is still required for ESD-prone, isolated (high-voltage, low-nose, RF), and dynamic sections of the circuitry, as well as the environmental range expected (i.e. if there is a chance the circuit could ever exceed an altitude of 3000m, then design for it.)

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  • \$\begingroup\$ I'm a bit confused about 'uncoated' vs 'polymer coating'. Does soldermask qualify as coating (it's a polymer after all) or do they mean conformal coating? I would expect three different values for bare copper vs soldermask vs soldermask+conformal coating \$\endgroup\$
    – Gnarflord
    Commented Feb 16, 2023 at 18:52
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    \$\begingroup\$ I am curious about your "altitude of 3000m" exemple : what happens then? \$\endgroup\$
    – Olivier Dulac
    Commented Feb 16, 2023 at 19:44
  • \$\begingroup\$ Gnarflord, I take "permanent polymer coating" to be akin to total encapsulation as the specs are nearly as good as "internal conductors." Olivier, at high altitudes there is less air to prevent arcing. Imagine a 275V trace with a clearance of 1.25mm for an LCD CCFL backlight. This is fine for sea level (B2.) But have a mountain climber take that device with them (B3) and this is not enough clearance distance.; the trace will likely fail. \$\endgroup\$
    – rdtsc
    Commented Feb 16, 2023 at 21:39
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    \$\begingroup\$ Above 3000 m the air pressure is less and Paschen's law applies en.m.wikipedia.org/wiki/Paschen%27s_law \$\endgroup\$
    – D Duck
    Commented Feb 16, 2023 at 23:22
  • \$\begingroup\$ @rdtsc I've studied the standards in depth, and I'm 100% confident that soldermask definitely qualifies as "polymer coating" under IPC. But IPC is NOT a safety standard, only a PCB quality control standard. If there's a shock hazard, it needs to be certified according to IEC standards, more rigorous electrical spacing is required. For more information, see my answer Does recommended creepage distance apply to copper planes under soldermasks?. \$\endgroup\$
    – 比尔盖子
    Commented Feb 17, 2023 at 6:54
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The IPC (formally the Institute for Interconnecting and Packaging Electronic Circuits) standards discuss minimum trace spacing and trace widths for circuit boards. They contain a lot of great information, but the standards are not free.

The Saturn PCB toolkit distills many of the IPC standards into what you need, and it is available for free:

https://saturnpcb.com/saturn-pcb-toolkit/

enter image description here

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The standards and toolkit are a good starting point, but what you find in the standards may be costly to to manufacture. PCB fabricators typically have a chart detailing minimum trace widths, trace spacing, minimum drills, ... For example:

https://docs.oshpark.com/services/two-layer/

Some fabricators will list standard and advanced services:

https://www.4pcb.com/pcb-capabilities.html

Anything from the standard service column doesn't add cost to your PCB. If you need narrower traces, tighter trace spacing, smaller holes, etc. than what is available from standard service, you can go to advanced service, but expect to pay more. If you have questions, email the fabricator. They want happy customers and will work with you.

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If you use OSHPark, you can download a "design rules" file for various CAD editors (like eagle) and place it in the correct folder, some pcb houses have a page dedicated with the design rules and you need to make you own design rules file, like www.Aisler.net, but also provide a file.

https://community.aisler.net/t/pcb-design-rules/41

https://github.com/AislerHQ/aisler-support/blob/master/design-rules/autodesk-eagle/aisler_2_layer_complex.dru

https://docs.oshpark.com/design-tools/eagle/design-rules-files/

once loaded in your CAD software, the software will automatically warn you about clearance and also indicates where.

enter image description here
https://101eagle.blogspot.com/2009/12/eagle-net-classes.html

Eagle also allows you to assign "clearances" per type of "net" class. You don't need to worry, the program itself will indicate where you go wrong.

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