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I want to design a PCB with few "low dropout linear voltage regulators", which would be used to power some sensors we are building. None of the parts on the PCB is expected to do any high speed switching. The sensor is on a separate board, and the power from the PCB is routed through SMA cables to the sensor. (The power requirements are low ~mW, and SMA is used just as an additional shielding). Sensor operates at 10 MHz, and I need the supply to be clean upto few 100 MHz. The regulators will be decoupled by low ESR capacitors and will be powerd from batteries.

I wanted the PCB not to pickup any external interference and was suggested a 4 layer design, where the stack was 1-GND, 2-Signal, 3-Signal, 4-GND. But, many online forums reccomend against this, and they prefer the reference planes at the layers 2 and 3.

  1. Can someone experienced in this field give their views on this? I dont mind if reworking the board would be impossible.

  2. Should I add a grounded copper pour on the layers carrying the signals?

  3. How closely should the via stiching be done? (Some of the major noise sources I get are at 2 MHz, 100 MHz-FM and 555 MHz).

Please let me know if further informaton is needed. Thanks.

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    \$\begingroup\$ 1. The main problem is your components normally mount on the exposed top and bottom layers. This would interrupt the ground plane. Thus why it is more usual for the planes to be inner layers. 2. Depends. Normally you’d not do a pour on the top and bottom as it is interrupted and you need to ensure you have no islands that are floating. For RF you pour specific sections. 3. Stitching interval depends on the frequencies. There are online calcs for that. \$\endgroup\$
    – Kartman
    Feb 18 at 6:21
  • \$\begingroup\$ @Kartman 1) The components that I need to mount are very small. (5mmx5mm roughly) Will such small opening on the outer GND planes reduce its effectiveness in shielding the inner traces? 2) Should I pour on the signal planes if I can mate all of them at GND? 3) From some sources, ~5cm spacing is suggested. I'll put 2cm spacing to be on the safer side. \$\endgroup\$
    – user32335
    Feb 18 at 7:30
  • \$\begingroup\$ You must define signal impedance to get meaningful answers. Both on the sensed node and of the sensor output. \$\endgroup\$
    – tobalt
    Feb 18 at 7:53
  • \$\begingroup\$ Is there a reason not to have regulation at the sensors you are building? \$\endgroup\$
    – Andy aka
    Feb 18 at 8:39
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    \$\begingroup\$ The bigger picture is what I'm trying to see and, that includes why you think having external regulators is more important to cost compared to the clear EMI problems external regulators can bring when remotely sited. Compare that with your PCB question and it seems to me that you might be focussing in the wrong place. \$\endgroup\$
    – Andy aka
    Feb 18 at 9:28

2 Answers 2

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I know you want the board to not pick up external interference but don't forget the board itself can generate interference if your layup is not great. Which it won't be if you have broken ground planes. From your comment about how cutouts in the ground plane for components might affect the shielding, it seems you are completely focused on shielding and giving no thought to the presence (or lack thereof) of an unbroken ground plane.

I suppose if you have solid plane underneath the components and literally only have cutouts for the pins you might get away with it if your components are few since it would largely be like a regular plane with vias going through it. But the devils is in the details.

Also remember that the signal layers in that layup do not share the same reference plane and you will need to accommodate for that when signals move between the signal planes or else you will just generate more EMI.

This is from Henry Ott's book EMC Compatibility:

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You may be interested in these for comparison:

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But man, it feels nasty.

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    \$\begingroup\$ Ott advocates GND on 1 and 4, but also doesnt discuss the problem with the large holes in the planes. Therefore I think GND on 2 and 3 is better. For low impedance signals and low density, the outer layer signals are completely fine. \$\endgroup\$
    – tobalt
    Feb 18 at 8:17
  • \$\begingroup\$ @DKNguyen The power supply is DC. I just need a very clean DC power from the board. The sensor might inject some noise back into the board, but I am uncertain of how strong it would be. As the signals traces do not switch fast, should I be worried about EMI created when singals move between planes? I only have very few components (close to 20 SMD components). Thanks for the very detialed answer. Which one of Figure 16-14 B and Figure 16-15 will have a superior shielding against external interferences? \$\endgroup\$
    – user32335
    Feb 18 at 8:17
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    \$\begingroup\$ @user32335 The power supply is not DC if you use it to power a 10 MHz sensor. Its only DC if you decouple the sensor and supply with a low frequency choke \$\endgroup\$
    – tobalt
    Feb 18 at 8:25
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    \$\begingroup\$ At those wavelength you only have realistically E field coupling on outer layers. If your signal impedance is low, the shielding will be equivalent regardless of signals on inner or outer layers. @user32335 \$\endgroup\$
    – tobalt
    Feb 18 at 8:30
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    \$\begingroup\$ @user32335 pour next to traces will have almost no coupling, so for EMI and noise it doesn't change much. Decide this based on manufacturing considerations \$\endgroup\$
    – tobalt
    Feb 18 at 8:41
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In most cases a stack-up with two GND planes should be superior to any other stack-up without two GND planes from an EMC perspective. Whether your GND planes are on L1+L4 or on L2+L3 doesn't make too much of a difference anymore in many cases.

One additional benefit of having GND on L1+L4 is that you can stitch them together around the periphery of the board to create a Faraday cage. Then again signals on outer layers with a close-by GND plane shouldn't be very good antennas anyway (receiving or transmitting). So the actual difference in EMI performance might be negligible.

Personally I always default to GND being on L2 and L3 on four layer boards, unless their is a strong compelling reason to do otherwise.

I wouldn't bother with GND pour in the signal layers. What you can do is pour power on the signal layers. Maybe in a way they overlap so you can connect them with vias. But that depends a lot on your application.

Regarding stitching vias the most important thing is to have a close-by return GND via for every signal via, if practicable. This is probably enough stitching so you might not need any additional GND vias.

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  • \$\begingroup\$ +1 The "Then again..." nicely reveals the core of this question, IMO. I guess one of those "compelling reasons" for outer GND is if you have a really high impedance node that you want to shield from picking up external E field. Personally I have only encountered such a situation when the node was in a metal chassis anyway. \$\endgroup\$
    – tobalt
    Feb 18 at 18:24
  • \$\begingroup\$ @feynman Thanks for the concise and informative answer. \$\endgroup\$
    – user32335
    Feb 19 at 5:17

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