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I have a four-layer board with a substantial 48 V section. According to IPC-2221, I can use a clearance of less than 6 mil between tracks on inner layers, but I need 24 mil clearance on the outer layers. If I go to Board Setup > Net Classes, I can create a separate class for my 48 V nets, but there is only a single option for "Clearance", which applies to all four layers. Is there some way to change the clearance independently for different layers?

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  • \$\begingroup\$ I believe you can with custom design rules, though perhaps that would be a good feature to have in the standard interface. Maybe bring it up on the KiCad issue tracker? \$\endgroup\$
    – Hearth
    Feb 18, 2023 at 18:43

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Unfortunately, Kicad doesn't support this yet. One thing to consider for your particular use case:

External clearance only needs to be that high on uncoated external layers. If you are in a situation where you care about IPC-2221, it is very likely that you also care about longevity, reliability and other factors. Under those conditions it is very likely that you want to conformal coat your assembly, which allows for much lower trace spacing at 48V.

See https://www.smps.us/pcbtracespacing.html

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