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I am trying to understand why edge triggering is preferred over level triggering. In my book it is not explained clearly. After searching online I came to know that edge triggering is insensitive to glitches whereas level triggering is sensitive. What does it mean?

Also I am not able to understand the following: "If the clock is level sensitive, the new \$Q_n\$ can rush through the logic network and change the output. To avoid this we need an short pulse to capture the output and hold it constant. But such short pulse is not easy to create, hence we go for edge triggering. The feedback problem is solved because there's insufficient time for the new output to race back to the input within duration of a single rising edge"

I did not understand why the output would not rush in level triggering and why we need a short pulse to hold the output.

Secondly, the feedback problem, since the level triggering duration is long as compared to the edge triggering, in the case of the former, the output would be fed back again to the input and it will keep doing this as long as the clock is active. What is the feedback problem?

But how will it be solved in edge triggering? If the time for falling or rising is very short, how will the output be able to propagate through all gates? Is it like, once edge triggering is applied the output will be propagate through all gates and next inputs will be considered only at the next clock edge ?

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    \$\begingroup\$ "once edge triggering is applied the output will be propagate through all gates and next inputs will be considered only at next clock edge" - bullseye!! \$\endgroup\$ – Wouter van Ooijen Apr 13 '13 at 9:59
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Although an edge is a well-defined moment in time, it is not true to say that level-triggering also does not have a well-defined moment in time. It does. There is a well-defined moment in time when the level of the clock falls, the inputs to the clocked circuit are sampled, and further changes in inputs are no longer admitted.

The issue with level triggering is that while the clock level is high, inputs change the outputs. In circuits that have feedback (the outputs are connected back to the inputs) level triggering causes chaos, because the level is wide enough (half a clock cycle) that the output can feed back to the inputs within the same period.

So by the time the well-defined moment occurs when the clock falls and every device is supposed to snapshot and hold it state until the next level, chaos has already occurred and the circuits are in unpredictable states. This is unacceptable. In sequential circuits, we want the outputs produced in clock period \$t\$ to only come into consideration for computing the states of clock period \$t + 1\$. We also want the nice property that we can slow down the clock, and not have the sequential circuit break. In level triggering, slowing down the clock works against us. The more we slow down the clock, the more time we allow for unrestricted feedback.

The first obvious solution which suggests itself to shorten the level to the point that it is impossible for unwanted feedback to occur (and to keep the "on" level short, even if we arbitrarily slow down the clock period). Suppose that we pulse the clock from 0 to 1 and back to 0 very quickly, so that the clocked devices accept their inputs, but the outputs do not have enough time to race through the feedback loop to change those inputs. The problem with this is that narrow pulses are unreliable, and basically require a response that may be several orders of magnitude faster than the clock frequency. We might find that we need a pulse that is a nanosecond wide, even though the system runs at only 1 Mhz. So then we have the problem of distributing clean, sharp, sufficiently tall nanosecond-wide pulses over a bus designed for 1 Mhz.

The next logical step, then, is to have the devices generate the narrow pulse for themselves as the time derivative of the clock edge. As the clock transitions from one level to another, devices themselves can internally generate a short pulse which causes the inputs to be sampled. We do not have to distribute that pulse itself through the clock bus.

And so you can basically consider it all to be level-triggered in the end. Edge triggering is a trick to allow devices to create a very fine level trigger which is faster than all external feedback loops, allowing devices to accept inputs quickly, and then close off the entrance in time before their changing outputs will change the values of the inputs.


We can also make an analogy between the "enable" signal (level triggered clock) and a door on a craft which holds air pressure. Level triggering is like opening a door, allowing air to escape. However, we can build an air lock which consists of two (or more) doors, which are not open simultaneously. This is what happens if we split the level clock into multiple phases.

The simplest example of this is the master-slave flip-flop. This consists of two level-triggered D flip flops cascaded together. But the clock signal is inverted, so the input of one is enabled while the other is disabled and vice versa. This is like an air lock door. As a whole, the flip flop is never open so that the signal can freely pass through. If we have feedback from the output of the flip-flop back to the input, there is no issue because it crosses to a different clock phase. The end result is that the master-slave flip-flop exhibits edge-triggered behavior! It's useful to study the master-slave flip-flop because it has something to say about the relationship between level and edge triggering.

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    \$\begingroup\$ Level-sensitive multi-phase clocks avoid the "chaos" problem if no latch's output feeds back to its input without going through a latch which is sampled on a different clock phase. Such designs can have some advantages when interfacing processors with things like asynchronous memories, since the time between the leading edge of one clock phase and the trailing edge of the next may be arbitrarily divided among the time required to route and output the address, the access time of the RAM, and the setup time for the processor's data input. \$\endgroup\$ – supercat Apr 22 '13 at 20:25
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    \$\begingroup\$ @supercat As a familiar example, the master-slave flip-flop might be considered an example of multi-phase clocking. The master and slave are on opposite phases, and so the same condition holds if there is feedback: it goes to a different phase. I should add this to the answer to round it out. \$\endgroup\$ – Kaz Apr 22 '13 at 20:58
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    \$\begingroup\$ +1 air lock analogy. I never heard anyone explain it this way but it makes perfect sense. \$\endgroup\$ – ajs410 Apr 22 '13 at 21:20
  • \$\begingroup\$ @ajs410: Another analogy I like is a clockwork escapement. The pendulum is connected to two arms, each of which can either allow the escapement gear to move freely or block it the next time it reaches a certain "phase". For proper operation, the arms must be adjusted so that there's no time when both arms would let the gear spin. Without that constraint, the mechanism would spin wildly out of control. \$\endgroup\$ – supercat Apr 22 '13 at 22:52
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To understand why edge triggering is preferred, imagine an 8-bit adder hooked up to a register, constantly adding 1 to the value of the register, with a push-button wired to the enable pin of the register.

If the enable pin of the register is level-sensitive, then the contents of the register will constantly increment for the duration of the button press. The next state of the register will not be deterministic for a given press of the button. This is because the adder can increment the register many times before you can remove your finger - in other words, the feedback leaves the register and makes it back to the adder too quickly.

If the enable pin was edge-sensitive instead, the contents of the register would increment exactly once each time the button was pressed, no matter how long the button was pressed for (assuming the input is properly debounced). It would be impossible for the output of the register to make it back to the adder in time for any non-deterministic behavior.

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Like others said, the edge is a very specific moment in time. We all know that digital circuits can go through glitches where an output of a gate is wrong since only a few of its inputs have reached it, the other signals are on its way and are taking longer because of the longer path (electricity travels quite fast but still 3x10^8 m/s takes a bit of time to go around wires). If we have a level trigerred unit, it's output will be effected by glitches. With making things edge triggered we have a very narrow window in time where "things can happen", in other words the circuit will only change its state (the values at different wires inside the circuit, including the output) at certain well defined instants in time. Please note the phrase "instants in time" down since this is what defines the behaviour of a sequential circuit made up of flip flops.

At this point you will not be aware of something called as "timing analysis" but I will explain a bit. When we make digital circuits, we want to simulate them to see how they will behave and if this behaviour fits what we want it to do. In timing analysis we check if the signals are able to reach at a certain point in the circuit within the required time. If they are too delayed than the circuit will not work correctly. By using edge triggered circuit blocks instead of level triggered, the timing analysis becomes very easy since we know exactly when things can happen in the circuit. This means that design of the circuit becomes easier also. Remember that in the real world you will come across level triggered latches very rarely.

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Edge-triggering is good for clocks, because it allows the value output by a latch in response to one (e.g. rising) clock edge to be used in the computation of what it should do on the next rising clock edge. If one is constructing a sequential circuit such as a counter using a number of edge-triggered latches, one may arbitrarily mix fast and slow logic components provided that, for every possible path, the propagation time minus the amount by which the receiving latch's clock lags the sender's, is guaranteed to be greater than the receiver's hold time, and the cycle time plus the amount by which the receiving latch's clock lags the senders, minus the propagation time, is guaranteed to be greater than the receiver's setup time.

By contrast, constructing a circuit to count pulses on a single input without using edge-triggered latches would require certain guarantees about the relative speeds of some parts of the circuit. A common approach used to be to convert an incoming clock (ClkIn) signal into a non-overlapping pair clock signals (Phi1 and Phi2). Phi1 is true when ClkIn is high and has been high for some guaranteed-minimum time. Phi2 is high when ClkIn is low and has been low for some guaranteed minimum time. When ClkIn switches from low to high, Phi2 will go low before Phi1 goes high; likewise when it switches from high to low. One could construct a counter by having two sets of latches (which I'll call Count1 and Count2). Whenever Phi1 is high, Count1 latches Count2. Whenever Phi2 is high, Count2 latches (Count1+1). If Phi1 and Phi2 were to both go high at once, or with too little time between them, the counter value would become indeterminate, but provided the proper separation is maintained, the counter will operate very nicely. Two-phase-clocked systems often have a rather generous amount of separation engineered in; provided everything is fast enough, such separation can avoid problems with clock skew.

Internally, many edge-triggered latches may be thought of as a master/slave pair of latches which are wired so that the master latches the input whenever the clock is in the state before the edge, and the slave latches the master when the clock is in the state after. The signals feeding the two latches need to have a suitable relationship, but if they're produced in the same vicinity as the latches, one need not over-engineer the amount of separation nearly as much as would be necessary if the two clock phases were sent over a wider area.

Note that while edge-triggering is good for clocks, there are other purposes for which it is less good. It's sometimes advantageous for periodic events into interrupts provided that no two events share the same edge-triggered signal. Edge-triggering is lousy for shared interrupts, and in some cases can be problematic even with unshared ones unless there's a way to poll the state of the interrupt wire. Level triggering may also be advantageous in cases where a strobe signal will be active on the same cycle as some information which should be latched, but where the information has a longer computation path than the strobe. If the information is something like an address for an asynchronous memory chip, having it become available sometime during a clock cycle may be better than having it wait until the beginning of the next clock cycle.

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Although other answers have covered almost everything there is to say about your question, to make it more clear I have added a few diagrams and a short explanation.

Imagine you want to design a circuit that includes some sort of a feedback. Say A = A.B(basically an AND gate with a feedback). If you implement it using a simple level sensitive latch that stores the value of A, your circuit will look something like this enter image description here

This can create a problem. When the clock is high, the latch becomes transparent, and the AND gate computes the new value of A and B. But the value is fed back to the latch, and since the latch is still transparent (CLK is still high), the new value of A AND B is computed. This is what is commonly referred to as a Race Condition, which creates glitches (unexpected highs and lows in the output) that you mentioned.

One solution to this problem would be to keep the CLK pulse very short, short enough that once the output of the AND gate is generated, the latch is deactivated before the value is backpropogated to the input again. It should be intuitive to see why this may be difficult to achieve. It would depend on the switching speed of the latch (finally, a latch is also made out of combinational gates), the length of the wire, and hundreds of other parameters.

A second more feasible option is to use an edge sensitive element (a flip flop in this case), which is basically a couple of latches connected in a very clever way.

enter image description here

Basically, when the CLK signal is high, latch U1 is transparent, which brings the logic value at the A input to the output of latch U1, when the CLK signal is LOW, the latch U2 becomes transparent, and a new value of A AND B is calculated. But this value will propagate to the input of the AND gate only when the latch U1 becomes transparent (CLK is HIGH), and consequently latch U1 becomes transparent (CLK is LOW). Which is basically equivalent to saying that the circuit is now edge sensitive (the output value changes only at the negative edge of the clock).

This avoids the problem of Race Condition explained earlier, and that is why level triggering is preferred over edge triggering.

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