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In the STM32H750IBK6 REV V, what is the maximum FMC_CLK to run SDRAM?

The datasheet has two different values (for the rev V and rev Y IC revisions).

What is the safe area of operating FMC CLK with SDRAM?

screenshot of datasheet revision history page.

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2 Answers 2

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For a Rev-V IC, the value from page 262 of the STM32H750 datasheet applies, so the limit is 110MHz with Vdd in the range of 2.7V to 3.6V: enter image description here

For an older Rev-Y IC, the value from page 154 of the datasheet applies, so the limit would be 100MHz with Vdd in the range 1.8V to 3.6V: enter image description here

If for some reason you don't believe the datasheet then you could probably contact your ST FAE for confirmation.

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For the STM32H750IBK6, the manufacturer's most recent datasheet informs me that the revision code is marked on the IC package. See section 8 of the datasheet (starts on page 311) to see where to find the revision code (either V or Y) on the device markings of your particular package.

Once you determine which revision you have, the information will be found starting on either page 137 (revision Y) or page 243 (revision V).

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