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I have a normal CMOS inverter designed in LtSPICE. Here are the details: Gate voltage: Pulse- Minimum=0V, Maximum=1.8V, Delay=0s, Rise time=0.1us, Fall time=0.1us, Ton=0.5us, Total time=1us. Supply voltage= 10V DC

When I measured the output, it is showing 9.8V during logic low. However, ideally, it must go down to zero, right? I wanted to know why is it not going to zero?

EDIT: Hey, sorry I wasn't able to comment back. The initial problem was that when Vdd=10V and Vg is 1.8V, why isn't the output not going down to zero. When I changed the Vdd to 1.8V such that both the supply and gate are of same amplitude, the circuit was working.

Why did it not respond in the same way earlier? What can be the reason?

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    \$\begingroup\$ 1.8 V isn't enough to count as logic high on a standard cmos input. \$\endgroup\$
    – Hearth
    Feb 22, 2023 at 6:49

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If your supply voltage is 10V, then 1.8V is definitely not enough to surpass the NMOS threshold to switch it on. Your CMOS has been desgyfor high voltage and their threshold voltages are definitely higher than 1.8V.

Try 5V or higher at least.

Or better yet, do a DC sweep at the inverter input from 0 to 10V to see where the switching points are. You should be able to plot a vout vs vin curve telling you that information.

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    \$\begingroup\$ 5V on input would (ideally) keep both NMOS amd PMOS on by equal amount, making the output 5V, and making current flow from supply to ground. The input voltage must be high enough to turn off PMOS. \$\endgroup\$
    – Justme
    Feb 22, 2023 at 7:12
  • \$\begingroup\$ When I changed the Vdd to 1.8V such that both the supply and gate are of same amplitude, the circuit was working. \$\endgroup\$
    – mANmAN01
    Mar 31, 2023 at 5:14
  • \$\begingroup\$ @mANmAN01 You can also keep the 10V VDD and sweep the input from 0 to VDD, it should work as well. \$\endgroup\$
    – Designalog
    Mar 31, 2023 at 5:16

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