I am trying to understand what SPI mode this LTC2640 (DAC IC) uses. The datasheet is either not consistent, or I am missing something. Page 16 of the datasheet:

LTC2640 SPI mode

You see, the SCK clock here lasts from the one sampling point, up to the next sampling point, so it lasts 2 bits total.

But at page 20:

LTC2640 SPI mode again?

The SCK lasts for only 1 sampling point, and goes to 0 when the bit transmit finishes.

Now, I use an ATmega328p IC, and I tried all the 4 modes available to see which one works properly. I figured out that only one of the modes I tried does not work; mode 1 does not work. The rest of the 3 modes do output the two voltages I am testing them with (2.5 V and 1.25 V).

Below is a screenshot from the datasheet of the ATmega328p, page 175, the available SPI modes, and the one I crossed out is the one that does not work.

Atmega328p SPI modes

Now the problem is, the other 3 modes might "seem" to work, but what if I lose the LSB bit from using the wrong SPI mode and instead of 1.2500 V the DAC outputs 1.24999 V, but I am unable to see that on the multimeter? After all, it's a 12-bit DAC, and I use its internal reference point of 2.5 V. Thats 0.61 mV per step.


  1. It is possible that the SCK clock might last for 2 sampling points? Could they have programmed the IC to do that, even thought that is not how the official SPI protocol is defined?

  2. Which is the correct SPI mode of the LTC2640 DAC IC? (I use LTC2640HTS8-LZ12 in particular, but that should not matter.)


1 Answer 1


In figure 1 the greyed out areas mean don't care, not that there is a bit transition indicating a second bit that should be sampled on the falling edge of SCK. Figure 1 is a timing diagram that shows the setup time (t1) and hold time (t2) that your data must match. Changes outside that time are irrelevant. Traditionally, the sender of the data (and SCK) would change the data on the falling edge of SCK to meet the setup and hold times (although this not always the case).

In your particular case, the LTC2640 is using mode 0 SPI as it is sampling on the rising edge of SCK and expects data to change (setup) on the falling edge of SCK. The other modes only work through luck and any data would be very suspect.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.