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How do I build an 7-bit reduction operator (i.e. a device counts the number of 1s in the input) ?

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    \$\begingroup\$ This very much depends on the "component" set to build from: please edit into your question. A single 128×3 bit ROM would do nicely… \$\endgroup\$
    – greybeard
    Commented Feb 23, 2023 at 8:31
  • \$\begingroup\$ If time is not "needed", use an MPX and a counter (?) \$\endgroup\$
    – Antonio51
    Commented Feb 23, 2023 at 10:58

3 Answers 3

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We can't tell you that without knowing which technology / "parts/components" you have at hand.

If you need to wire this together from bijunction transistors, the answer will look very differently from you being asked to write RTL for a digital ASIC with a specific set of standard cells, and it will look yet different from you being asked to design things in a higher-level hardware abstraction for FPGAs.

So. General methodology:

  1. Actually write down your problem: That means writing down your inputs, i.e., all bitlines, including how they are clocked, and the expected outputs, including clocks.
  2. Get an overview of the tools at hand. For example, check whether you can just make a 7-bit address, 3 bit output lookup table with a clocked input; if you have proper logic synthesis tools, chances are, no matter how you write down the solution to the problem, your synthesizer will build "the right thing" out of it.
  3. break down your problem into smaller, manageable components. Maybe you know how to make a 4-bit reduction operator? Great! So do that, 2 times (might need you to "invent" an 8. bit that's always 0), and then, find a way to combine these? This might be a natural approach on some platforms, or totally strange on others, again, depending on the components you have at hand.
    This also highlights that you have the chance to make decisions on combinatorial depth and pipelining early on. You can combine all the 4-bit reductors in one cycle, or you can have registered outputs and move the combination into the next cycle. That will make your circuit have latency, but faster.
  4. write out your solution in a block diagram. Implement that block diagram, block for block. Test each block for correctness, before plugging them together.
    How that implementation looks: totally up to your platform and your approach.
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  • \$\begingroup\$ This answers closer to "How do I go about designing an implementation of X" than "How do I build X". Not saying the former isn't what Nidhi has wanted to know/profits from. \$\endgroup\$
    – greybeard
    Commented Feb 23, 2023 at 13:30
  • \$\begingroup\$ @greybeard hm, in that case, consider "4." from my answer the answer to their question, and everything before necessary prologue :) \$\endgroup\$ Commented Feb 23, 2023 at 13:40
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If "time" has no importance, something like this could be used ...

For only 7 inputs, last input (MSB) is 0. Can be "extended".
Made with "standard" devices.

enter image description here

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You tagged .
A (1-bit) full adder takes three inputs and computes their binary sum: as sum bit weighed \$2^{k+0}\$ and a carry bit with weight \$2^{k+1}\$.
Other interpretations of this result include that it's the count of inputs that are "1", which is why the same circuit may be called a counter (a combinatorial one),
or that it uses fewer outputs to represent something about its inputs, which accounts for designation as a compressor.

With 7 input signals, you can start by feeding 2*3 to two full adders:
this results in 2 outputs of weight 2¹ and 2+1 of weight 2⁰: a reduction from 7 to 5.
Going on, you need to take care to consider signal weights.

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