I'm designing a desktop PC motherboard with AMD Ryzen™ 9 7940HS.
We have an extension board similar to this one that performs negotiations with USB-PD charger and provides 20 V constant voltage to the platform. This board is designed by outsource company, and we don't want to interfere with it.
The 20 V is not guaranteed to be supplied after certain threshold, and we want to do the gating on the platform itself.
To be accurate, we want a circuit that passes voltage and current after the voltage reaches 17 V or more. Below 17 V, we don't want to deliver voltage to the system.
NOTE: The platform takes the 20 V and uses DC-DC to create 3.3 V and 5 V and other voltages for the CPU.
The main consideration of making sure only high voltage (17 V and above) is delivered to the system, is the fact that allowing low voltage at startup can allow high current to the CPU, and we don't want this risk. This idea is based on the fact the USB-PD Charger doesn't provide 20 V immediately like normal PSU, but it starts with lower voltages (5 V/3 A) and then goes up based on negotiations.
I found a gating circuit concept on the internet and tried to simulate it, and I wanted to know how much it fits my goal:
- V1 goes from 0 to 20 V (x-axis)
- We can see that around 16.8 V the FDC638P P-channel MOSFET is open.
I have few questions regarding this circuit:
- What is the need of using NPN bipolar junction transistor and not regular MOSFET? Is it for power considerations?
- Is 5 Ω load realistic to simulate for high current situations for CPU? (4 A and above)?
Note 1: I'm trying to make a simulation with a CPU load that has 35-54 W default TDP
Note 2: In this simulation the load seems to consume -4 A * 20 V =~ 80 W
- Is FDC638P suitable for situations where current can reach 5 A and 6 A spikes?
- Are there recommended chips that has all this circuit integrated? where I can configure it to pass voltage only when VIN >=17 V? (maybe more cost effective than my own circuit)
Update 1: Considering the devices suggested in the solution, I decided to use MIC2754 with a voltage divider that gives 2.93 V when VIN_ALW = 17 V:
I want to make sure that the transistor I picked: BSL307SP is suitable for my application. and that I picked the right place for the 17V_VOUT.
Assuming that threshold is met, and considering VOL(HV#)_MAX = 0.8 V, the P-channel MOSFET VGS = 0.8 V - 17 V = -16.2 V.
Looks like at such VGS at this graph passes really high current, and that contradicts the fact that the system can use up to 4-5 A.
Note 1: According to my previous simulation, seems like when the switching is done, the VDS on the transistor falls back to low voltage (about 320 mV). With such VDS, any VGS above threshold seems to be good for passing current which makes it a good switch. But what explains the VDS falling to such low value?
Note 2: this reminds me of what I learned back in university 5 years ago, that PMOS is good for transferring logic "1", and NMOS is good is good for transferring logic "0", where here we relate to analog voltages, and according to this we expect that the drain voltage be very close to 17 V, am I right?
Note 3: I still didn't understand the purpose of MCR708A SCR and the 1k and 22 Ω resistors, but I'm reading the datasheet of MIC2754 to hopefully understand
Update 2: I added a follow-up question regarding the solution that suggests using TL431.
Update 3: Regarding the solution that suggest using LM393 Compactor, I interested in replacing the M1 (IRF9530) since it has a big package (TO-220AB). I want an SMT P-MOSFET and also give it an option of cooling (for example I can take 5mm x 6mm as maximum size). I got stuck at what Power Dissipation parameter I need to choose regarding my application.
With the suggested solution that uses IRF9530, when VIN=20V, the VDS reaches about -485 mV at -3.903 A (Rds_On = 124.2 mOhm).
P = I^2 * R = (3.903)^2 * 124.2 mOhm = 1.89 W
I have been grabbing my head around the fact about how this P-MOSFET is providing 20V to a platform that has a CPU with TDP of 54 Watt, and the MOSFET itself dissipates only 1.89W, what I'm missing here?
Is the idea here that the P-Mosfet is just a gate with small resistance, and the USB-PD charger is the one responsible for providing the 54 Watt and the rest of power consumption by the platform?
Reminder: The platform takes the 20 V and uses DC-DC to create 3.3 V and 5 V and other voltages for the CPU.
Note 1: The application is an Industrial PC Desktop that should work at a 45 °C Ambient temperature, our thermal design makes sure that the enclosure doesn't go up beyond 70 °C, and we want ICs that still function perfectly with maximal junction temperature 100 °C. Note 2: Eventually I decided to place AOD4189 in my design.