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I have a question regarding this circuit as a basic (!) discrete MOSFET driver switching circuit:

enter image description here

Points I do understand:

  1. Because the MOSFET is most likely a non-LL-MOSFET, we need higher voltages on the GATE-pin in order to charge the internal capacity of the MOSFET to minimize R_(DS,on).
  2. Therefore a NPN transistor would be ideal (with R4 and R5), to switch the voltage on the gate pin with the input voltage of the circuit and GND.
  3. R6 is used to limit the possibility of a floating gate pin.

Question:

But why do you want to use the PNP transistor Q2? Which purpose does it have in this exact circuit? Wouldn't it be sufficient to only charge and discharge the gate pin via the NPN transistor connected to the MCU?

Thankful for an explanation on this circuit regarding the PNP-transistor.

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3 Answers 3

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Simply, you can get a faster rise-time this way. Whether that's important, depends on the MOSFET, what kind of load is attached, and how fast it should be switched.

Conversely, the single-NPN version has fast fall-time and slow rise. Or vice-versa if a P-ch MOSFET is used (given some other considerations: performance is generally ~2.5x poorer than NMOS, and assuming the load can be common-ground instead).

We can address these by "boosting" the pull-up/down resistor with an emitter follower:

NPN gate driver

(Resistor values are unimportant.) Note that when Q1 is off, the equivalent circuit is R1 supplying Q2 base. Base current depends on the voltage drop from +V to Vo, and emitter current is about hFE times larger (and shifted down a VBE). Basically the emitter looks like an hFE times smaller pull-up resistor, for no cost to Q1's on-current -- efficient.

This is roughly equivalent to the NPN + PNP case, though it saves a BOM item (fewer unique parts are required).

Or we can boost both ways, replacing the diode with a PNP emitter follower to boost discharge current:

Complementary emitter follower gate driver

This allows less current in Q1 for a given falling speed.

Note that the Q1 B-E resistor might not be needed: when the signal source is a CMOS output pin (typical these days), it has a nice low VOL, so Q1 will be discharged adequately in the low state (i.e., VBE(off) ≪ 0.7 V). (It does help with ensuring an "off" level from a tri-state source, such as an MCU during reset/initialization.) The base voltage divider motif does allow faster switching. Optimal switching is with the divider values set for a Thevenin voltage of about 2 VBE(on). So from a 5 V logic source, 10k + 4.7k is pretty reasonable for example. A speed-up cap can also be placed in parallel with the series resistor (your R4), typically 10-100 pF.

We can further improve it by replacing the pull-up resistor with a current source, so it pulls up equally as strongly across the whole voltage swing, rather than with a decreasing current.

The current itself can also be switched, to save on power dissipation, in which case the circuit starts looking a lot like a CMOS logic circuit (complementary yes, but in bipolar instead!); but then two level shifters are needed, and an inverter, and... it's a lot of components just to drive a gate, and I would definitely reach for a proper gate driver IC before going to those lengths. :)

Images from:
Driving MOSFET from MCU with BJT
Limiting the base current to BJTs in Gate Driver circuits

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    \$\begingroup\$ in case there is a possibility of MCU being OFF when +12V is present, Q1 B-E resistor will help define the B-E voltage. \$\endgroup\$
    – sai
    Feb 26, 2023 at 15:09
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    \$\begingroup\$ @sai Or during initialization (typically tristate on reset), good point. \$\endgroup\$ Feb 26, 2023 at 15:18
  • \$\begingroup\$ Simply speaking: Charge and Discharge speed during high frequency switching of the MOSFET gate pin via separate NPN and PNP transistors without resistors in the collector/emitter path is preferred instead of diodes or just pulldown-resistor in combination with only 1 NPN transistor. Is this an accurate summery for the overall problematic in the circuit mentioned in my question \$\endgroup\$
    – Dakalaom
    Feb 26, 2023 at 15:41
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    \$\begingroup\$ @Dakalaom Not quite: the configuration matters as well as the lower resistance. The emitter follower arrangement is good for pulsed current like this. These also don't show a dedicated gate resistor, which is usually preferred for several reasons (but can be quite small, ~ohms, giving fast results still). And an NPN (common emitter) would have a pull-up resistor for collector load. \$\endgroup\$ Feb 26, 2023 at 16:04
  • \$\begingroup\$ What would be the difference to a common collector; thus PNP on high-side and NPN on low-side, besides changing the logic (on/off). Would there be any other benefits/disadvantages? Because you say, that the circuit above is especially great for pulsed current. \$\endgroup\$
    – Dakalaom
    Feb 26, 2023 at 17:26
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You don't need the PNP if you don't need it to turn on fast. With suitable resistor choices, the PNP provides a large turn-on current. To make it fast without the PNP, the collector resistor for the NPN needs to be small, wasting lots of power and making lots of heat when the MOSFET is off. That's generally impractical.

This circuit, with only a resistive pull-down, turns off slowly.

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Few points to consider as to why PNP might have been used

  1. When MCU is OFF, what do you want the gate of the MOSFET to be? If you remove the PNP and drive it with NPN only, the MOSFET gate will be at 12V when MCU is OFF. If you have the PNP stage, it will be at 0V when MCU is OFF.

  2. What is the max VGS of the MOSFET that you are using? With NPN stage only, like mentioned in point 1, VGS can go to 12V. Whereas if you use PNP stage, the max VGS is set by the resistor divider R3-R6.

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