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I'm working on a problem from an ETH Zurich course. They want you to build a transistor-level CMOS implementation of a XOR gate.
My attempt at this is the following:
The given answer is this:
Why is theirs so much more complex? I feel like I'm missing a standard rule that prevents mine from working, but I don't know what.
Have you tried simulating this design to see what it does? (I would not recommend actually building it.)
Recall the basics of n-channel MOSFETs: they will conduct when the voltage at the gate (\$V_G\$) exceeds the voltage at the source (\$V_S\$). by a certain threshold voltage \$V_{TH}\$. In other words:
$$ V_G - V_S > V_{TH} $$
though often you'll see it as \$V_{GS} > V_{TH}\$, with \$V_{GS}\$ just a shorthand for \$V_G - V_S\$.
And with drain, gate, and source as follows:
simulate this circuit – Schematic created using CircuitLab
In addition to the n-channel device, there's the p-channel device. Note that the P-Channel MOSFET is inverted, and the source is pointing up: since in English things come in from the "source" and go out through the "drain", a helpful mnemonic is that the P-channel device sources Positive charges from the Positive rail. For completeness, note also that the p-channel MOSFET equation is slightly different: to turn on, \$V_G\$ must be less than \$V_S\$ by a specific threshold.
For PMOS:
$$ V_S - V_G > V_{TH} $$
(though on the datasheet, instead of \$V_{SG}\$ you'll likely still see \$V_{GS}\$ and a negative \$V_{TH}\$).
Back to your XOR gate. As others have noted, you've left a floating node, so I've taken the liberty of adding a pulldown resistor. This resistor "pulls down" the M5 gate, holding its voltage at ground (i.e. zero volts) unless there's some external force (i.e. M1 and M2) actively pulling it up. I think this was your intent. Without this, any stray electrical noise or charge could couple to the "floating" gate on M5, turning it on or off unpredictably.
Here's the schematic, which you can simulate with the link below it. Right-click on the switches and click Edit parameters to open and close them. Note that I'm using 10 V as a logic HIGH; that's just to make sure these particular transistors turn fully on and simulate correctly. Different transistors will have different threshold voltages, and work at different logic levels.
In your design, assuming digital logic, there are four possibilities: A and B can either be grounded, or at VDD. Let's talk through all four cases.
Case 1: A and B are both grounded. B being grounded means M2 is not conducting; its gate and its source are both 0 V. M1 is also not conducting unless its source is somehow less than zero -- but there's no voltage below zero in this circuit, and in any case the body diode in M2 will ensure it doesn't get too far below zero.
In fact, M1, M2, M3, and M4 are all in "common drain" or "source follower" configuration. Looking at the equation above, you can see that the gate voltage must be above the source voltage for current to flow. In other words, for the transistor to turn on, the source voltage must be significantly lower than the gate voltage. In circuits that have a known drain voltage and a known gate voltage, this "forces" the source voltage to be some amount below the gate, since that's a requirement of it being on. The source voltage, in other words, follows the gate voltage -- hence "source follower".
But the gates are all at 0 V. The output would somehow need to be less than 0 V if the transistors are meant to be on. This is impossible in this circuit, so we can conclude that M1, M2, M3 and M4 are off.
Finally, since M2 is off, the pull-down resistor pulls M5 off, and therefore all five of your transistors are off. The output is floating. (Without the pull-down resistor, the M5 gate would also be floating, and any stray charge or noise may cause M5 to flip on or off at any time.)
In the simulation, the characteristics of the particular transistors I've chosen are holding the output at a few microvolts (transistors will conduct small amounts even when off), but the output impedance is so high that if you were to add a load, the output could be anything. (This, by the way, is the "loading effect" -- when the input impedance of the next stage is too low relative to the output impedance of this stage, it will actually pull the output voltage one way or another. But that's another story for a different question.)
Case 2: A is at VDD and B is grounded. If A is at VDD, both M1 and M3 will conduct as source followers. Each transistor's gate is at VDD, so each source will be some drop below VDD. Since B is grounded, M2 is not conducting, so M1 is not actually doing anything. M4 and M5 are also off, so the output is determined entirely by the source follower M3, and the output will be some level below the VDD input. In the schematic above, the simulator pegs it at 6 V -- well below the 10 V we would like it to be! Imagine what would happen if there were a second identical logic stage after this one: the A2 gate would only be at 6 V, and though VDD would still be 10 V, the source inside the second logic gate, and therefore that gate's output, would drop even further! Not good!
Case 3: B is at VDD and A is grounded. M2's source starts at ground due to the pull-down resistor, so the gate going high means that M2 will have a conductive channel. However, M1 is off, so that just pulls M1's source to 0 V. There's still no path for VDD to get to M5's gate, so M5 remains off. M3 is similarly off, but now M4 conducts at the same (source follower) voltage as M3 did in the above case. Again, the simulator shows 6 V.
Case 4 (the explodey case): Both A and B are at VDD. This is the fun one. With M2's gate at VDD and its source pulled down to ground, M2 conducts. This pulls down M1's source, which allows M1 to conduct. They're still source followers, so they don't pass VDD directly through, and thus they don't pull M5's gate all the way up to 10 V. However, they can pull it high enough that M5 is now conducting. (This is why I put VM2 in the circuit above -- according to the simulator M2's gate is now 5.993 V, i.e. it's seeing the expected 4V voltage drop from the M1 source follower + a small voltage drop due to the extra resistance inside the fully-on M2 transistor.)
Since M5 is now deep in its conducting region, it's pulling the output to ground.
M3 and M4 are also conducting, as source followers. They'll be trying to pull the output to 6 V, even as M5 is trying to pull the output to ground.
Put an ammeter in there and you can quickly see the problem:
9.2 amps. In a 10 V circuit, that's 92 W. Stick that in a kettle and in a few minutes you'll have tea. The two halves of the circuit are fighting, with incendiary results. You've let the magic smoke out.
To build a logic gate, you want a circuit that is either pulling the output strongly to ground, or strongly to VDD. And never both at the same time.
To accomplish this, CMOS circuits are made from transistors in "common source" configuration and not "common drain." Instead of connecting drains to power rails, we connect nMOS sources to the negative rail and pMOS sources to the positive rail. Each pMOS in the top half has a complementary nMOS in the bottom half (hence CMOS), connected to the same input signals. When that input signal is low (ground), its nMOS cannot conduct; when the input signal goes high (VDD), its pMOS cannot conduct. (If the input signal were somehow at VDD/2, it may turn both on, so we try to ensure the signals rise and fall quickly.)
Common-source amplifiers provides lots of gain. Even if the incoming signal is noisy and hits 1 V, the nMOS won't turn on much (if at all) and the pMOS will still be strongly conducting; the output will still be high. The transition from high to low is quite sharp, and aside from the middle, very stable. This is what the input and output of a basic CMOS inverter looks like: very stable when the input is near GND and VDD, with a rapid transition between the two states in the middle. (Pardon the MS Paint graph.)
This allows even marginal input signals to drive the corresponding transistors fully-on or fully-off. Helpfully, this also means that CMOS logic is "restoring" -- even if the input signal is attenuated over long wires, the next stage will see the full voltage again.
The common-source configuration does this well: when the input is GND, the top (PMOS) half is conducting because its \$V_{TH}\$ equation is satisfied, and for the same reason the bottom (NMOS) half is off. And when the input is VDD, the bottom half is on and the top half is off. With fast-enough switching time (to avoid the undefined state when the input is halfway between the two) nothing gets shorted, nothing blows up, and the output is always at one of the two rails.
This is why the actual given CMOS XOR is so complex. It needs to function with only PMOS transistors in the top half and NMOS transistors in the bottom half. If you do a similar analysis to what I've done here, with the circuit you were given, you'll see that it meets all of the necessary criteria.
Your design leaves the transistor at the output with a floating input. Green means on, red means off. My assumption, in your design, is that all the transistors are active high . The "Given solution" has some bubbles at the inputs of some transistor, I assumed those are active low. The ones without the bubble are active high.
