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In my current project I am using a STM32H723ZG Nucleo board on a custom shield PCB with two AD7380 ADC's which amount to 4 signal channels. The goal is for the next PCB revision, to read out all 4 channel in sync with a sampling rate of 100kHz to 200kHz(more if possible), do some DSP calculations each sampling cycle, run a Decimation to have an appropriate data rate to send the data out over some Bus. All on a completely integrated PCB, without a Nucleo Dev-Boad.

At the Moment the ADC's get sampled with a normal SPI connection one after the other using the SPI4 peripheral for channel "1+2" and SPI1 for channel "3+4". Both SPI peripherals run at 40MHz each with hardware chip select. Both ADC's run in "single-wire-mode" with a sampling frequency up to 100kHz, however i did manage 200kHz at some point but with almost no time to do DSP calculations.

Previous ADC data receiving scheme

However there are a few problems I would like to fix with the next version. The way I see it I can do a few things to improve sampling frequency and DSP plus housekeeping time.

  1. Use the ADC's two wire (parallel) mode. This will improve the time spent receving data also by two.
  2. increase clock frequency for communication at best to the ADC's maximum of 80MHz again reducing the time spent receiving data by 1/2.
  3. Configure the interface such that both ADC's sample and send data at the same time and not one after the other.

Desired ADC data receiving scheme

I don't know how to tackle these problems mainly because of my lack of knowlege about the STM32H723 and Programming skills, hence this post. I thought about a few different ways, which maybe solve some or all my issues. But there are a few unknowns for me so I will list them below.

  1. Use 4 SPI peripherals which give me two MISO for each ADC and configure them as one master and three slaves when receving data. When configuring the ADC's switch to two master SPI's and do it as before.

Problem:

  • there will be the speedlimit of at least the max SPI clock around 133MHz/2 for SPI1 but even worse for SPI4. Tests showed I could run around 40MHz in a stable manner.
  • How and when can I service the slave's SPI data when the Master SPI itself gets Interrupt triggered from a timer.

  1. Use the OctoSPI to receive the Data from all channels in parallel and do the bit sorting in code using masks or union bitfields. This would be able to run at much higher clockspeeds such that i can get to the 80MHz ADC limit.

Problem:

  • I don't know if one can use a OctoSPI Peripheral in such a way, since all examples I could find did some conection to a flash or something.
  • How to configure the peripheral eg. as dual Quad or one Octo?
  • What problems come from the fact that this peripheral is in the D1 memory domain, where as the normal SPI is in the D2 domain especially if I want to use the DMA channels from D2?
  • Can the OctoSPI peripheral be used alone or do i need to use two normal SPI's to configure the ADC's too?

  1. Someone suggested in the ST community to look at the PSSI periperal, which seems to to do just what i need. Basically a simple SPI with a configureable number of dataline's. Again with the possibility to achieve max ADC clockspeed.

Problem:

  • It seems that the peripheral can not generate a clock and receive Data (correct me I simply don't know).
  • In combination with the point above, do I need normal SPI's to generate the clock and to configure the ADC's here too? this would limit me again to the SPI clock limit.

  1. Tell me somthing even better.

Right now I am working a the new schematic and this is one of the bigger problems which I need to fix in this revision. Therefore I tried to use OctoSPI with a Nucleoboard and some wires connecting to the ADC on the shield, but with no success. I have read parts of the reference manual for the PSSI interface but not about its registers and what they do. All I found on the internet did not fit my problem so far.

All in all I think there has to be a way to make this happen with this big MCU that runs up to 550MHz, I simply don't know how because I lack the programming skill and experience with this MCU.

I hope I made my point clear and someone might be able to point me in the right direction, at best with a small example :)

Best Cem

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  • \$\begingroup\$ Are you using DMA for the SPI? \$\endgroup\$
    – Voltage Spike
    Feb 27, 2023 at 21:13
  • \$\begingroup\$ You can speed up any bus by trading off signal swing about threshold with pull-up/down resistors so it does not have as far to go. It is inefficient but effective. \$\endgroup\$
    – Hoagie
    Feb 27, 2023 at 22:30
  • \$\begingroup\$ I was not able to get DMA up and running and honestly i still dont know why. My guess is that it has something to do with the memory domains and the memory protection unit (MPU). However my idea is to use DMA to unload the CPU and build up a data processing pipeline with the build in filter co processor FMAC. As for the signal swing sure i thought about it, but in the end the limiting factor will be the maximum SPI frequency which is dependent on the AHB bus and can therefore run at max 133MHz/2 = 66.5MHz. The ADC can run up to 80MHz. \$\endgroup\$
    – Cem E.
    Feb 28, 2023 at 6:49
  • \$\begingroup\$ Aside from anti-alias filtering, what DSP do you need to do prior to decimation, and why can't it be done after decimation? \$\endgroup\$ Feb 28, 2023 at 18:33
  • \$\begingroup\$ The system to measure has an inherent high pass property, which results in non accurate representaion of the signal compared to the actual input after some time. To extend this time to a certain degree without loosing high frequency information, I apply an inverse digital high pass filter. This should me more accurate when doing this on the higher sampling rate. However we are talking about a first order high pass correction which is not that much to calculate. \$\endgroup\$
    – Cem E.
    Mar 1, 2023 at 8:20

1 Answer 1

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Lets do some math 550MHz/200kHz = 2750 clock cycles for processing one sample between ADC samples. If you have two ADC's then you would have about half that. It seems doable to do a small decimation of several samples (like 8 or 16) and sample that data at 200kHz.

It's going to be difficult to get the ADC's running faster than 20MHz if they aren't on the same PCB, with termination (put a NL cap on the end of the SPI bus on the ADC side and compensate the clock and data lines), you will also need to keep wire/trace inductance low and capacitance of the line low to achieve rates faster than 20MHz, +50MHz will be difficult, even small amounts of capacitance will smooth out the clock.

The OP does not mention anything about DMA (direct memory access), this will be necessary if you haven't done it. The problem with not doing DMA is you will be wasting many clock cycles on transfering data which ties up the host processor, whereas with DMA the spi port is setup and it automatically transfers the values to memory.

One thing you might want to consider is just using the ADC eval kit, which uses an FPGA and will have exact timing.

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