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In the datasheet of the 18F4620 and others, section 9.0 (page 91), I read:

The PIC18F2525/2620/4525/4620 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress.

I see that when a low priority interrupt service routine is running and a high priority interrupt occurs, the high priority ISR will be runt.

However, what happens when a high priority interrupt occurs during a high priority ISR? Or, when a low priority interrupt occurs during a low priority ISR?

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I believe the answer is... nothing.

When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit.

When an interrupt occurs, the respected GIE bit is cleared.

The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The “return from interrupt” instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used) which re-enables interrupts.

You have to clear the peripheral interrupt and upon your exit from your ISR, it will set the respected GIE bit.

If you look at Figure 9-1, it shows the logic behind it all. enter image description here

When your interrupt occurs, GIE is cleared, and so that OR gate wont be true and will not trigger a jump to your high priority interrupt vector.

What would most likely happen is when you exit your ISR, you would jump back into service a different interrupt.

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