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I am integrating a non-isolated DC/DC converter from Mornsun in one of our designs.

We are trying to stick to the typical application schematic:

DC/DC Typical Application

However, two questions dictated by the limited space we have on our board arise:

  1. We need a 100 µF input capacitor as per the schematic. However, we are also using a transistor to switch ON/OFF the DC/DC converter (and have a very low quiescent current, the OFF current of the DC/DC converter being 2 mA typical, which is way higher than what we need).

We'd ideally put the capacitor before the switching MOSFET (N-channel driven by a high-side gate driver) like so:

Input CAP Before

Would there be any reason to believe it would be different from this set-up:

enter image description here

We're also integrating an ideal diode on the output and are asking ourselves the same question about the positioning of the output bulk capacitor.

  1. Now onto the second problem:

A 100 µF, 75 V capacitor (and in a lesser way, the same for the output capacitor) is quite big and tall and we don't have a lot of space available. We'd like to go for 10 x MLCC 10 µF caps, but given they are not electrolytic, is there some degradation in performance to be expected? From my understanding, it's more of the contrary since the MLCC usually have a lower ESR/µF at a given voltage, but I feel like we have a blind spot somewhere.

enter image description here

A last element, here is the schematic for "improved" EMI suppresion : enter image description here

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    \$\begingroup\$ MLCC suffers from significantly larger capacitance change when a DC voltage is applied vs electrolytic - this means that you will likely need more than 10*10uF MLCC. I assume the connection to GND on the mosfet gate is a mistake. There will be a difference between the two configs - the first config has the ripple current going through the mosfet (medium resistance/inductance) and the fuse (high resistance) - this will degrade the effective performance of the capacitor and might even trigger the fuse (depending on the characteristics). Why do you want to do this? Are you worried about inrush? \$\endgroup\$
    – BeB00
    Feb 28, 2023 at 9:40
  • \$\begingroup\$ Hi @BeB00, Yes, mistake for the mosfet gate connection. The main reason for the first config (which is the one we favor) is only because of available space. The cap would stand directly in the way of another component of the device so we cannot put them there... Another way that might work would be to split the 100µF in 4 x 22µF for example. \$\endgroup\$ Feb 28, 2023 at 9:52
  • \$\begingroup\$ One thing I am not sure I understand though : shouldn't the ripple current and voltage be attenuated by the cap on all the line, regardless of whether it's positioned before or after? \$\endgroup\$ Feb 28, 2023 at 9:58
  • \$\begingroup\$ That's a Recom part as far as I'm aware and, it's an isolating type (unlike your title). \$\endgroup\$
    – Andy aka
    Feb 28, 2023 at 10:31
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    \$\begingroup\$ Your schematics are wrong; why do you have gate connected to "+48V GND"? What does the FAN7371 bring to the party? \$\endgroup\$
    – Andy aka
    Feb 28, 2023 at 10:49

1 Answer 1

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My answer is: it depends.

The capacitor usually is used to smooth out the voltage ripple, and - smaller ones - filter out noise, etc. In an ideal world, if your power supply internal resistance is almost zero, and your current leads and routes are wide enough to have a zero resistance you even do not need a capacitor. Just try to imagine how far away are you from this.
In your case, the FET implies even at a completely open state a resistance, on which you will have a voltage drop, if this is a switching power supply with switching frequency this voltage drop will have that periodicity, its amplitude will depend on the load resistance. And this is just the FET...

What I suggest:

  • If it is possible try to use a different DC/DC converter that has EN pin and lower quescient current. Cutting off power from DC/DC convert via FET is not an elegant solution, and even I am not certain that it will work in all cases.

  • If the previous solution is not possible, I would keep the electrolytic cap. before the FET, and I will try to add as much as possible capacitance to the input of this DC/DC converter (after the FET). Maybe will it work.

Not at least do no forget to add 100nF caps.

Update: Do not forget about the leakage current of the FET in off state. Maybe on certain circumstances it is enough to make strange strings.

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  • \$\begingroup\$ Thanks for the answer @NNN123. Unfortunately we have not identified a suitable part with low Iq and EN pin. When you mean "before the fet", you are referring to the 2nd schematic, right? The one with the cap at the closest to the DC/DC? \$\endgroup\$ Feb 28, 2023 at 11:31
  • \$\begingroup\$ Regarding the 100nF, I guess those can be MLCC? If I look at the "improved" schematic, I'm seeing 4,7µF caps but not 100nF. What could be the reason for putting 4700nF instead of 100nF? \$\endgroup\$ Feb 28, 2023 at 11:35
  • \$\begingroup\$ "we have not identified a suitable part with low Iq and EN pin" -- the part in your schematic has a CTRL signal? \$\endgroup\$
    – Matt S
    Feb 28, 2023 at 14:03
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    \$\begingroup\$ No, I mean add 100uF capacitor before the FET and add as much are you able to add after the FET. \$\endgroup\$
    – NNN123
    Mar 1, 2023 at 9:34

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