I was hoping I could get some verification on my flyback design process, and some questions answered.

The document I was following is from Fairchild, AN4137, and the steps below essentially outline its design guide process.

  1. Find Vin_Min

The flyback I am designing is being fed from a PFC Bus, so, 400 VDC with +/- 2.5% ripple, giving a Vin_min of 390 V.

  1. Determine Dmax and VRO (output voltage reflected to primary side)
  • Using $$VRO = \frac{D_{max}}{1-D_{max}}*Vin_{min}$$
  • Plugging that into $$V_{ds} = Vin_{max}+ VRO$$

Change the value of Dmax so that Vds is 65% to 70% of the Vds rating of the MOSFET you are planning to use.

  1. Calculate Primary Inductance

$$L_{m} = \frac{(Vin_{min}* D_{max})^2}{2 * P_{in} * F_{sw} * K_{rf}}$$

Because this is a DCM design, Krf = 1.

Pin = Pout/eff

  1. Calculate Ipr_pk (primary peak current through Lm)

This allows you to calculate the minimum number of primary turns to achieve a certain Bmax as seen below

  1. Calculate Np_min

$$Np_{min} = \frac{L_{m} * I_{pk-pk}}{B_{max}*A_{e}}*1E^{+6}$$

Ae is a cross-sectional area of transformer in mm

Bmax is a value you choose, say 0.2 T.

From here calculate the turns ratio and the secondary turns for the regulated winding, and use that winding for calculating other secondary windings.

Something larger 5. Gap Length Based on Bmax

$$\mu_{e} = \frac{\mu_{i}}{\mu_{i} *\frac{L_{g}}{L_{e}} + 1} (Equation 6)$$ $$B_{actual} = \mu_{o}*\mu_{e}*H (Equation 7)$$

Where, Lg = gap length, Le = MPL (magnetic path length), H = N *I /Le, and $$\mu_{o}= 4 * \pi*10^-7$$

If you substitute mu_e from equation 6 into equation 7, and solve for Lg, you get:

$$Lg = \frac{\mu_{o}* \mu_{i} * N_{p} * I_{pr-pk}}{(B_{m} * L_{e}) - 1)} * (\frac{L_{e}}{\mu_{i}})$$

mu_i is in the initial permeability read off the datasheet.

This equation tells you the gap length required to meet your flux density Bm requirement. Knowing this, you can then use equations 6, and then assume a gap length larger that what you calculated, get a mu_e, and recalculate the inductance using the equation below.

$$L_{mag} = \frac{\mu_{o}* \mu_{e}* N^{2} * A_{e}}{L_{e} + L_{g}}$$

If you choose a gap length where L is now below your spec, increase N by some number, choose an integer value, and go through the process again to get a higher inductance closer to your requirement.

So, does that sound correct?

Another question I have with this process that I'm concerned about is that in the beginning they get you to find VRO based on Dmax (that you choose). But, with a multiple output flyback, how good of an estimation is that VRO, since, at this point the equation I referenced in step 2 doesn't account for any secondary voltages. How does that equation represent the reflected output voltages? Or am I missing something and their procedure is fine?

  • \$\begingroup\$ I would start with circuit design parameters such as ~Vin, ~Vout and switching frequency. calculate turns ratio and necessary Webers from there, then infer the necessary core size. \$\endgroup\$
    – tobalt
    Mar 1 at 6:10
  • \$\begingroup\$ Check your calculated results using a simulator if you want strong confirmation that you have done the process correctly. Also, can you use Latex mark-up language. Does "mew" = \$\mu\$? \$\endgroup\$
    – Andy aka
    Mar 1 at 9:21
  • \$\begingroup\$ @Andyaka I didn't know how to use that Latex language but I just re-wrote the equations in it, should be much more readable now. I ran the flyback in PSIM assuming all the power running through the regulated winding, given the steady-state biasing parameters and the output voltage and peak current through Lm correlate quite well with the calculated values. The thing I haven't used with PSIM is the magnetic circuits. Do you have some intuition, or able to address, my last question about VRO? \$\endgroup\$ Mar 1 at 19:41
  • \$\begingroup\$ @RogerDodger good job on the latex and note that \$\cdot\$ or \$\times\$ = \$\cdot\$ or \$\times\$. Good job on the simulation too but, I think you need to model the inductors as not 100% coupled as this produces an unwanted flyback spike on the primary that can damage the transistor. In other words you might need a "spike catcher". TBH I didn't understand what the VRO bit was about. \$\endgroup\$
    – Andy aka
    Mar 1 at 20:06
  • \$\begingroup\$ @Andyaka thanks. Yea, I usually do an ideal analysis, make sure the DC operating parameters are working, then add the non-idealities. I usually start leakage somewhere between 5% to 10% of the reference inductance (this one being magnetizing inductance). Here's another website that is doing a QR flyback design (electronicsbeliever.com/…), and they are using Vref as what I call VRO. Could you take a look and see how they are ensuring Vref is relevant and actually is being designed for? \$\endgroup\$ Mar 1 at 20:29


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