6
\$\begingroup\$

I have to design a multilayer Board (8 Layer). This is a part of 4 PCBs in a product with plastic enclosure. The high speed signal on PCB are Ethernet, USB2, LAN and UMTS integrated modem. Product dimension is 4" x 4" x 2" . I'm undecided between two stackup tipology EMC oriented (the product will be tested in laboratory for CE mark).

STACKUP (A)

  • Signal1
  • VCC
  • GND
  • Signal2

  • Signal3

  • VCC
  • GND
  • Signal4

Routing layer is formed by pairs signal1-signal2 or signal3-signal4.

High-speed signals are buried between planes, therefore the planes provide shielding to reduce the emissions. In addition the board uses multiple ground planes, thus decreasing the ground impedance. But (this is my doubt) in this configuration is necessary a capacitor (VCC to GND) near the signal via, in order to provide an adjacent return path for the current.

So i want use this configuration

STACKUP (B)

  • Signal1
  • GND
  • Signal2

  • VCC

  • GND

  • Signal3

  • GND
  • Signal4

Routing layer is formed by pairs signal1-signal2 or signal3-signal4. Here high speed signals have the same reference, but i have only one buried capacitors and I fear that the signals are poorly shielded.

How is critical the return current in Stackup A? I suppose that the best in my application is stackup (B).

Thanks and best regards.

\$\endgroup\$
5
\$\begingroup\$

But (this is my doubt) in this configuration is necessary a capacitor (VCC to GND) near the signal via, in order to provide an adjacent return path for the current.

Yes. For stackup A, you will want a nearby decoupling capacitor wherever your signals transition between Signal1 and Signal2 or between Signal3 and Signal4.

Not only do these capacitors take up space and cost money, but also, they force your return current to take a longer path than it would have to if it could just transition from one side of a copper plane to the other, so they introduce some EMI risk.

[With stackup B] I have only one buried capacitor

I wouldn't worry too much about trying to make buried capacitance. Answering a recent question I worked out roughly the value of capacitance you can build in to a board. You have a multilayer board, so you can have much smaller plane-plane distance than the guy who asked that question, but you also have only 4 x 4" of total area to work with ... I don't think you'll achieve more than a few nF of total capacitance with that arrangement. Of course it will be very high quality capacitance, effective to very high frequencies, but realistically a factor of 2 difference in the capacitance value isn't going to make or break your design.

[Also, for stackup B] I fear that the signals are poorly shielded.

In either stackup your signal1 and signal4 traces aren't well shielded, and your signal2 and signal3 traces are fully enclosed by ground planes. I feel these two situations are essentially equal.

In a comment to another answer, you also mention,

I have many power source (+12V, +5V, +3.3V)

This means you'll likely need or want to break up your VCC "planes" between nets, and so there will be slots in those plane layers. That makes them much harder to use for return paths, as you do for signal1 and signal3 traces in stackup A.

Overall, I'd recommend stackup B.

\$\endgroup\$
  • \$\begingroup\$ Thanks you very much !! These answers are very useful for me, because confirm doubts and remove misgivings. Surely, after all considerations, i will proceed with the Stackup B without any doubt. I'll try to avoid cross net over split for hig speed signals in all plane. Furthermore, I will use a number of vias to connect all GND layers (2nd, 5th and 7th). I have other questions that I hope you have the patience to answer, but if necessary I will open other posts. Best Regards \$\endgroup\$ – Neutrino Apr 15 '13 at 21:07
0
\$\begingroup\$

I prefer stack B and I would do my best to get as much of the Vcc layer onto spare areas of the signal layers. This means that more of VCC layer can be used for GND.

I am assuming you having components only on the top layer (signal1 layer)

\$\endgroup\$
  • \$\begingroup\$ Thanks Andy aka for your reply. No, i have components and connectors in top and bottom layer. I'll try to cover every unused area with power plane, to obtain a decupling area. I have many power source (+12V, +5V, +3.3V). \$\endgroup\$ – Neutrino Apr 15 '13 at 10:46

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.