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I understand that power rails provide the energy required for a circuit to function. Intuition tells me there must be at least two types of rail, one providing power and another taking it away.

But I don't understand how these rails feed power through CMOS devices or which rail is used to power which CMOS device.

What are the types of power rail, and how do they get the circuit to perform computational work?

I've added a CMOS inverter for reference. I couldn't a functional circuit working in circuit lab. But this is my current understanding of the power rails and how they feed the CMOS devices in an inverter:

schematic

simulate this circuit – Schematic created using CircuitLab

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    \$\begingroup\$ Circuits don't usually do useful work (work being energy). Circuits can get hot and that would generally be regarded as non-useful work. So, can you clarify what you mean? The two nodes associated with a power rail don't transfer power in one wire and take it away in the other. They both equally transfer power/energy to the load. Maybe you are getting confused between current and power? \$\endgroup\$
    – Andy aka
    Commented Mar 2, 2023 at 10:42
  • \$\begingroup\$ I mean computational work. I've updated the question to reflect that. What do you mean they equally transfer power/ energy? Does that mean the current flows through both directions? Or does that mean both are required to send power through the circuit? \$\endgroup\$
    – Connor
    Commented Mar 2, 2023 at 10:56
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    \$\begingroup\$ Can you look up how a CMOS inverter works? It has two transistors, and four wires; input, output, supply and ground. \$\endgroup\$
    – Justme
    Commented Mar 2, 2023 at 10:56
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    \$\begingroup\$ @Connor please show a schematic of a CMOS inverter (even if it might be simplistic) as a reference point for making a basic answer. \$\endgroup\$
    – Andy aka
    Commented Mar 2, 2023 at 11:01
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    \$\begingroup\$ @Connor - One of the purposes of power (and return) rails in an IC is to provide a low inductance path for the fast edge-rate currents that flow when an output switches state. Are you familiar with the term Simultaneous Switched Outputs, better known as SSO? Look that up using your favorite search tool, and you'll find a lot of information as to the importance of low inductance PDNs (Power Delivery Networks), of which an IC's power rails are just a part of.. \$\endgroup\$
    – SteveSh
    Commented Mar 4, 2023 at 3:27

1 Answer 1

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The example you show has a CMOS FET pair, connected as an inverter, that provides paths to VDD or VSS (GND) depending on the input state.

Think of it as a single-pole, double throw switch that’s controlled by the input, that inverts. It is tying the output to VDD when the input is low, or GND when the input is high.

In other words,

  • Input high, lower n-FET has a positive gate-source voltage and turns on
  • Input low, upper p-FET has a negative gate-source voltage and turns on

This behavior is what enhancement mode FETs do. They’re normally off until they see an appropriate gate-substrate voltage, which turns them on. The gate-substrate bias enhances the channel between drain and source, allowing current to flow.

(Note: source is usually tied to substrate in logic. Otherwise the notion of ‘source’ and ‘drain’ is arbitrary: FETs can conduct in both directions. Transmission gates use this capability.)

The alternative MOSFET version, depletion mode, is normally on, then ‘pinched off’ (depleted) by the gate-substrate bias. You don’t typically see depletion-mode FETs used in logic today. In the past they saw widespread use as a pull-up for NMOS logic.

JFETs are inherently depletion mode, as they use a reverse-biased PN junction for the gate instead of an oxide insulator. This made them difficult to use for logic, but they are excellent for other uses, such as high-impedance amplifier inputs.

Here’s a paper that will give you more of a deep-dive into how MOSFETs actually work: https://web.stanford.edu/class/archive/ee/ee214/ee214.1042/Handouts/HO2mosphysics.pdf

The output could be a DC load (like an LED or a TTL logic gate, or a capacitive load like another CMOS input. So the FET pair, under gate voltage control, simply ties the load to either VDD or GND. It’s not more complicated than that.

None of this would be possible unless there were power rails present - not only to provide reference for the output, but also to provide gate-substrate bias reference for the FETs themselves so they can operate.

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  • \$\begingroup\$ Is the ground, \$V_{SS}\$, 0V or the negative of \$V_{DD}\$? \$\endgroup\$
    – Connor
    Commented Mar 4, 2023 at 6:32
  • \$\begingroup\$ Thank you btw, I thought I was using MOSFETs in my diagram, but if they're depletion mode won't that prevent my circuit from working? \$\endgroup\$
    – Connor
    Commented Mar 4, 2023 at 6:38
  • \$\begingroup\$ Yes, because depletion mode devices require biasing outside of the signal range. \$\endgroup\$ Commented Mar 4, 2023 at 19:23

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