The example you show has a CMOS FET pair, connected as an inverter, that provides paths to VDD or VSS (GND) depending on the input state.
Think of it as a single-pole, double throw switch that’s controlled by the input, that inverts. It is tying the output to VDD when the input is low, or GND when the input is high.
In other words,
- Input high, lower n-FET has a positive gate-source voltage and turns on
- Input low, upper p-FET has a negative gate-source voltage and turns on
This behavior is what enhancement mode FETs do. They’re normally off until they see an appropriate gate-substrate voltage, which turns them on. The gate-substrate bias enhances the channel between drain and source, allowing current to flow.
(Note: source is usually tied to substrate in logic. Otherwise the notion of ‘source’ and ‘drain’ is arbitrary: FETs can conduct in both directions. Transmission gates use this capability.)
The alternative MOSFET version, depletion mode, is normally on, then ‘pinched off’ (depleted) by the gate-substrate bias. You don’t typically see depletion-mode FETs used in logic today. In the past they saw widespread use as a pull-up for NMOS logic.
JFETs are inherently depletion mode, as they use a reverse-biased PN junction for the gate instead of an oxide insulator. This made them difficult to use for logic, but they are excellent for other uses, such as high-impedance amplifier inputs.
Here’s a paper that will give you more of a deep-dive into how MOSFETs actually work: https://web.stanford.edu/class/archive/ee/ee214/ee214.1042/Handouts/HO2mosphysics.pdf
The output could be a DC load (like an LED or a TTL logic gate, or a capacitive load like another CMOS input. So the FET pair, under gate voltage control, simply ties the load to either VDD or GND. It’s not more complicated than that.
None of this would be possible unless there were power rails present - not only to provide reference for the output, but also to provide gate-substrate bias reference for the FETs themselves so they can operate.