# How to calculate overall power efficiency of multi-stage BJT amp

I have a multi-stage BJT amplifier built using 2 NPNs and an initial N-channel MOSFET. The first BJT stage is a common-source amplifier with a bypass capacitor. The output stage is a emitter-follower amplifier. All the stages (and inputs and outputs) are AC coupled. I have attached an image for clarity.

I need to find the overall power efficiency of the amplifier for a given input signal (before the output is distorted).

I know that the overall power efficiency is given by (ac power delivered to load resistor / dc power generated by dc power supply), but using this is giving me a overall efficiency of 0.2% using a circuit simulator, which seems wrong to me. I am looking for clarification on my calculation of the power efficiency.

For how I calculated the efficiency see below:

• I found the ac power delivered to the load resistor using the RMS values for current and voltage observed for the load resistor (RL).
• I found the dc power generated by carrying out a basic dynamic dc simulation which displays the power generated by the 9V power source.

I understand that the AC coupling has removed the DC bias level which may have something to do with why my calculation is incorrect.

• Please ask a specific question Commented Mar 3, 2023 at 21:22
• I am looking for clarification on my calculation of the power efficiency Commented Mar 3, 2023 at 21:24
• Can you edit your question and put that in? Commented Mar 3, 2023 at 21:28

0.2% efficiency is within the realm of reasonable, depending on the output voltage.

Lets go through a mental thought process (answers will be very approximate)...

1. What is the DC quiecent current supplied by the 9V source? I come up with about 7.5 mA (I modified the values of your circuit to make it work for the parts I'm using). $$\ 7.5mA \times 9V = 67.5 mW \$$.
2. Lets say the output voltage is 1 VDC. That means the power dissipated by the 250 ohm load resistor is $$\ 1^2 / 250 = 4mW \$$.
3. Thus, you would suspect that the efficiency should be less than $$\ 4mW / 67.5mW = 5.9\%\$$.

Modeling your circuit in LTspice, I used a J111 for the JFET (you didn't specify the type of device, but generally you would use a JFET, not a MOSFET for this device). I had to adjust RS1 to bias the JFET properly.
I also changed R4 (your schematic reference) to bias the output transistor so it can drive the output load at 1 Vpp.
In the future, show the manufacturer part numbers you are using.

• Thanks for the thought process, but what do you mean by the output voltage being 1 VDC? Wouldn't it be an AC signal corresponding to the input? Commented Mar 4, 2023 at 10:34
• @tintins7a6164 1 VDC is simple to deal with in my limited mind. The end result of mental calculations, the quiescent power is much larger than the output power which gives an idea where the efficiency will end up, i.e., not very good. It is a good idea to have a feeling where the answer lies. If measurements don't jibe with approximations, you need to check things out (is the test equipment working properly, are the calculations right, circuit built right, circuit oscillating, ...). In your actual circuit, you need to deal with AC signals which is done in the simulation.
– qrk
Commented Mar 4, 2023 at 17:54