I've seen lots of questions here about various spikes/overshoots/transients when using MOSFETs but when I try to apply the solutions to my circuit I can't seem to apply them in a way that makes much impact.

I am trying to learn more about MOSFETs by creating a small RGB hub. The hub will ideally connect an LED strip to 2 separate RGB controllers and a microcontroller will be used to enable/disable the connection to each RGB controller. The RGB controllers are Low side switches, the RGB strip is 12 V common anode. Both the controllers and the strip are embedded in larger components so I am not sure of their composition, and they cannot be modified. All I know is that it is a low side switch and the LEDs I am trying to control draw up to 60 mA total. The microcontroller I am using is a Seeed Xiao SAMD21, with a PWM frequency of 732 Hz and a max GPIO current of 10 mA.

I have tried (possibly incorrectly) decoupling the voltage sources, adding RC snubbers, and various diodes in various places. All I've found to keep these spikes within safe regions is resistance, but my concern is that while the spikes are kept within an acceptable range, they remain proportionally large. I tried many different MOSFET models and they largely behave the same provided that the Vto value is sufficiently low.

My actual questions:

  • How would these spikes translate into the real world as opposed to a simulation? Are they likely to be smaller or bigger or similar?
  • It feels concerning that the voltage sources are affected by the switching of other voltage sources, specifically the impact of Vcon2 on the Vgpio sources. How is this happening?
  • What can/should I do to reduce these current spikes and protect the components that are embedded?

Pictured below is the circuit in it's simplest form to hopefully avoid confusion. I removed my attempts at decoupling and RC snubbing but left the gate resistors. LowSwitchSwitch1

EDIT: As suggested by the comments I have added inductance to many of the traces as well as decoupling caps and the spikes became 1000x larger, so I'm not sure if I did that right.


Additionally this graph shows that the GPIO pins are not enabled at the same time GPIOTiming


Added decoupling caps closer to the gates, this seemed to cut the spikes down about halfway. The transistors M2 and M3 still have some spikes, but they don't appear as dramatic as the GPIO spikes, and the load seems to behave ideally. I may still investigate other methods to protect the microcontroller. LowSwitchSwitch3

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    \$\begingroup\$ Replace the inductors with resistors and start with 100ohm then keep playing with the values. I see all your current measurements are for the independent voltage sources. Are you worried about spikes there, or are you also getting spikes through your loads (the resistors + diodes)? \$\endgroup\$
    – Ste Kulov
    Mar 5, 2023 at 0:08
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    \$\begingroup\$ The spikes are a function of the rise/fall time of your GPIO switching and the gate capacitance of the MOSFETs. You form an RC circuit with any equivalent resistance in series with the gate, so a larger series resistor would slow the charging of the gate and reduce the spikes. The gate charging is also going to depend on the load in the drain, which is why you get a similar effect when changing the load. The gate capacitance is weird and non-linear. It's also going to change quite a bit between MOSFETs, so only use the model of the actual part you intend to use. \$\endgroup\$
    – Ste Kulov
    Mar 5, 2023 at 4:01
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    \$\begingroup\$ Keep in mind that your model of your GPIO (independent voltage source w/ 10ns rise/fall time) is not a good model for a typical CMOS output. If you’re going to go into this detail of seeing how much current is being spiked at each transition, then you need to create a more accurate model of your actual GPIO. I personally don’t think your spikes are likely to be a problem, but if you want to do a more thorough analysis and make a better model you can look at the manufacturer’s website for IBIS models or you can do some bench testing/measurements to get some rise times and a Thevenin equivalent. \$\endgroup\$
    – Ste Kulov
    Mar 5, 2023 at 4:03
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    \$\begingroup\$ More info here on IBIS: electronics.stackexchange.com/a/573907 . Also, Getting rid of those caps is a good idea. A voltage source right into a capacitor doesn’t do anything except produce massive current spikes whenever there’s a high dv/dt (i.e. when your GPIO switches) \$\endgroup\$
    – Ste Kulov
    Mar 5, 2023 at 4:04
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    \$\begingroup\$ There are some conventions for schematics. Usually you draw NMOSFETs with their drains up and source down, because that naturally fits another convention of having the voltage drop from positive to negative, as you go down in the schematic. \$\endgroup\$
    – tobalt
    Mar 8, 2023 at 7:32

3 Answers 3


The MOSFET gates are tiny capacitances, which depending on the model, range from a picofarads to nanofarads. The AO4630 device has a gate capacitance of over 500pF. Every time one of your voltage sources transitions from low to high, or high to low, that capacitor is charged or discharged, requiring a flow of charge, electric current, onto and off of the gate. That momentary flow is what you are witnessing as "spikes" in your graphs.

This is necessary, since to raise the gate potentials to 3.3V, you must charge those little capacitors up to 3.3V, and to get them back to zero you must discharge them, and each of those operations requires current to flow.

Another way to imagine this is to treat each charging event (raising the gate to +3.3V) as transferring a small "packet" of energy to the gate capacitance, and each discharging event (lowering gate potential back to 0V) as removing that packet of energy from the capacitor. When moving energy electrically, this implies a current flow, and a potential difference to make it flow.

However you picture this in your mind, current flow is necessary. To understand what we can do to control it, and the consequences of controlling it, we can model it very easily, with simulations.

In the simplest, naive model, I use a step voltage source to charge a 500pF capacitor, and assume that all components are ideal, and all conductors have no resistance:


simulate this circuit – Schematic created using CircuitLab

The voltage across the capacitor, and current through it are:

enter image description here enter image description here

As the input voltage step rises, the capacitor has zero volts across it, and represents a short circuit to ground. If conditions were as I described them, ideal, this should result in infinite current flowing, for an infinitely short time, but the simulator can't do either of those things, and gives its best shot. Current is very high, over 1.5A, for whatever duration a couple of pixels represents on that graph.

Notice how the voltage across the capacitor rises instantly. In real life, there is resistance in that loop, represented by R, but we can introduce a resistance artificially (as you have done with R3 and R7 in your circuit). Setting R to 10Ω gives this result:

enter image description here enter image description here

Voltage rises more slowly, and you begin to see the classic exponential charge curve for a this ubiquitous source, resistor and capacitor arrangement.

Most importantly, notice how the current peak is much lower, 330mA. It immediately begins to decay, but current continues to flow for a longer duration.

Perhaps you start to get an intuition about what happens when you limit current by increasing R, but we can calculate the peak current using Kirchhoff's Voltage Law (KVL), and Ohm's law. By KVL we know that the sum of voltages across R and C must equal the source voltage. If we assume that the completely discharged capacitor has zero volts across it prior to the input step, when the step occurs, suddenly the resistor must have the remaining 3.3V across it, so:

$$ \begin{aligned} I_{PEAK} &= \frac{V}{R} \\ \\ &= \frac{3.3}{10} \\ \\ &= 330mA \end{aligned} $$

In the next couple of graphs, the three different colours represent R=100Ω (blue), R=200Ω (orange), and lastly, to mimic your own situation, R=1kΩ (tan):

enter image description here enter image description here

The duration of the current pulse widens with increasing R, but peak current falls. Commensurately, with less and less current to charge it, C takes longer to reach its ultimate 3.3V voltage.

If you're interested in the "energy packet" that I mentioned before, energy would be the area under the graph (integral) of power, where power is the classic formula \$P = I \times V\$ (\$V\$ and \$I\$ being the voltage across the capacitor and the current through it). I've plotted power vs. time here, for the same three values of R:

enter image description here

The area under each of those curves is the same. The same amount of energy is delivered to the capacitor in each case, the only difference being the rate at which that energy is delivered. The bigger you make R, the longer it take to deliver the whole packet.

However, most importantly, you must deliver the entire packet of energy, or your MOSFET won't switch on. And because that requires current flow, you cannot avoid current flow. Sure there are measures you can take to "shape" the flow of current, to reduce the initial spike, but the trade-off is that it takes longer for the MOSFET to make the transition between "off" and "on".

Just for completeness, not because it's important to your question, that energy, the area under those curves, is easy to calculate. Knowing the voltage \$V\$ that a capacitor \$C\$ is charged to, the energy \$E\$ stored in that capacitor is:

$$ E = \frac{1}{2}CV^2 $$

You can also find out the amount of electric charge it has "stored" \$Q\$:

$$ Q = CV $$

This might be useful if the MOSFET's datasheet contains information about gate charge, in Coulombs, for different channel states.

In a digital system, it is desirable to keep the MOSFET either fully on, or fully off, because during some half-on, half-off state, the MOSFET itself is dissipating power (wasting energy as heat) in its somewhat resistive drain-source channel.

In other words, if you want your MOSFET to switch quickly, you must accept that there will be large spikes of gate current. Instead of trying to suppress them, which would defeat the operation of the MOSFET, you may shape them, but not so much that the transition from off to on (or back) is too slow.

Another fact of life is that while on paper the gates are not coupled in anyway to anything on the other side of the gate, this very same capacitance that causes gate current is also responsible for coupling potential changes at the gate into the channel on the other side, right into whatever system is over there.

That's why you see some gate transitions for M2 and M3 "leaking" over to the gates of M5 and M1, and vice versa. It's a problem only if they are significant compared to the signals that should be there.

With all this understood, you can have a better grasp of another aspect of digital design, which is the need for power supply decoupling capacitors near sources like Vcon1 and Vgpio1. These current spikes are inevitable, and those voltage sources are drawing that current from the supply rails. In your simulations, you have spikes of a few milliamps, but in some systems that can AMPS. Any inductance in the power supply paths will make it impossible for the power supply to respond quickly enough to the sudden demands of such large amounts of current for such short durations.

That's why we place decoupling capacitors across the power supply pins of digital ICs, and you should do the same in any physical circuit you build. Put them across the supply as close as possible to any circuitry which drives MOSFET gates; they will act as a local source of charge (energy) from which the gate driver can draw, without causing huge dips in potential of the power supply paths further away.

Capacitive power supply decoupling is intended to mitigate issues like gate current spikes, and shoot-through. Instead of trying to eliminate gate current, mitigate the effects of gate current elsewhere.

  • \$\begingroup\$ Thank you for taking the time to provide so much information, ive been spending the day trying to wrap my head around it. I added decoupling caps to the Gates (rather than the gpios seen in the question), at 10nF this seemed to cut the current spike roughly in half, however higher and lower values seemed less effective. Would it be practical to try and displace the spikes from the gpio by using a transistor driver or voltage buffer? \$\endgroup\$
    – superN8
    Mar 9, 2023 at 2:23
  • \$\begingroup\$ @superN8 I'm confused about what spikes in particular you are trying to suppress, or even why you think they need suppressing. The only "problem" I see here is "bleed-through" from GPIO-side gate to CON-side gate, and vice versa. Is this what you are trying to reduce? \$\endgroup\$ Mar 9, 2023 at 4:04
  • \$\begingroup\$ Yes, mostly. Prior to this I had really only used BJTs, so when I attempted to use FETs as drop in replacements, the "Spikes"/Transients/(Is there a proper term I should use?) that were created along almost every trace seemed concerning, especially on the GPIOs and components that are loosely represented. Choosing a proper FET has also been daunting compared to a BJT, and some microcontroller GPIO pins are clustered with limited documentation. Essentially I just want to ensure that I am taking all necessary and reasonable precautions should I ever change the design, or add complexity. \$\endgroup\$
    – superN8
    Mar 9, 2023 at 18:52

In the simulation, there is no inductance or resistance in any of the wires. Capacitors and wires are superconducting. If you want to make the simulation behave like a real world circuit, then put in some trace resistance and inductance, something like 10mΩ and 10nH, that should smooth out the spikes some. Another thing is to put a cap to ground on the nets being switched in the pF to nF range.

Check the power on the mosfets, they shouldn't be very spiky. Another problem that you may be having is turning on two mosfets at the same time. Make sure you don't have crossover on the gate voltage and allow some time so both FETS are not turned on.

  • \$\begingroup\$ I made edits to the question to reflect your comment, not sure if I implemented your solutions correctly but it seemed to have the opposite effect I was hoping for \$\endgroup\$
    – superN8
    Mar 4, 2023 at 1:04
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    \$\begingroup\$ I think you are experiencing crossover, where both fets are on. See if this is the case and try and eliminate the problem \$\endgroup\$
    – Voltage Spike
    Mar 7, 2023 at 23:58
  • \$\begingroup\$ Superconducting wires would actually have inductance. spice wires just have 0 impedance. Current spikes in toggling voltages sources shorted with capacitors are also entirely normal and expected. \$\endgroup\$
    – tobalt
    Mar 8, 2023 at 7:27
  • \$\begingroup\$ Except the capacitors in spice don't have inductance and ESR unless modified, so those need to be put in if you want closer real world behavior in a sim \$\endgroup\$
    – Voltage Spike
    Mar 8, 2023 at 15:44

In the second attempt, your voltage sources are shorted by 10 nF caps each. When toggling the voltage source you get a large expected current spike.

Don't load voltage sources with pure capacitors. That is just bad practice.

In the first example, you are still in a similar situation. The capacitance is the gate-source-capacitance of the FET. The spike is smaller, because it us limited by the 1 kΩ resistors.

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    \$\begingroup\$ (The "mutual current spikes" that seem to have triggered the question should be due to the reverse transfer capacitance \$C_{rss}\$.) \$\endgroup\$
    – greybeard
    Mar 8, 2023 at 7:55

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