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This question is from a project of mine I have been working on for about 3 months now, and I reached a point where I was going to go the route of using an interrupt based handler for my packet receiver when I realized it was not working out successfully, so I switched to a polling approach and it seems to respond to movements and produce non zero results, but, there is the issue of errors. I have implemented a software routine in an embedded system to handle polling and outputting the received data to a terminal, output shows desired movement packets, but it also has quite a bit of what seem to be erroneous data such as detectable cases where bits are 1 when not allowed, or zero when they should be 1.

The mouse transmits 8 bit data packets with a parity bit, so is that something I can use to detect errors, and if so, is it a matter of requesting retransmit, or correction of the individual data burst contained in a single movement packet.

What should I be doing to ideally detect, correct for the data coming in? I do not have familiarity with error correction so that might be of use here if doable.

I am now disregarding the entire frame (4x 8 bits of data) if there are detectable error conditions. I haven't checked parity mismatch.

What can I do to correct for errors ideally? Or do I completely drop the data for that one instance of movement change that occurred? Unfortunately even at present dropping movement still shows values for the individual bytes of data at times that are not supposed to have an assigned value such as the z-axis where the value is not changing but I get a zero. I hope this is not due to my byte receiver misaligning with another byte in another frame without first getting through the previous frame....

Any help would be appreciated.

The current problem is the values of z are changing even when I don't move mouse wheel but just move the mouse x or y and there are present bursts of 4 bytes of data with issues maybe due to misalignment of bytes when I read in software.

See receiver module https://github.com/vahejab/arty_sv_sampler/blob/main/arty_sv_sampler.srcs/sources_1/imports/code_listing_sv/fpga_mcs_sv_src/hdl/mmio/ps2/ps2rx.sv

FIFO (with/without grey code counting - uart uses fifo with binary counting, and ps/2 uses counter with grey coding) https://github.com/vahejab/arty_sv_sampler/blob/main/arty_sv_sampler.srcs/sources_1/imports/code_listing_sv/fpga_mcs_sv_src/hdl/mmio/mmio_support/fifo/fifo_ctrl.sv

ps2_core.cpp https://github.com/vahejab/arty_sv_sampler/blob/3571d686f0f69c9b3cb114b845b666e1e04ba3f5/arty_sv_sampler.sdk/VC707_Application/src/ps2_core.cpp

See readme for more information https://github.com/vahejab/arty_sv_sampler

Top Level Elaborated RTL Representation Top Level Schematic

PCA9306 - The Level Shifter on the SparkFun PCA9306 Breakout Board

Level Shifter

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  • \$\begingroup\$ On further research, something tells me my present method of obtaining single samples per bit might be problematic. A link on error correction has led me to state this eecs.umich.edu/courses/eecs373.w05/lecture/errorcode.html however I do believe that mouse host gets a new bit works on edge transitions on a transmitted clock, I do have some interesting way of connecting to my system via a breadboard, a level shifter breakout pcb and 4 wires connected to the PS2/USB adapter. Presence of errors might be due to any unwanted noise, though I haven't verified. \$\endgroup\$
    – Vahe
    Mar 5, 2023 at 0:32
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    \$\begingroup\$ If the hardware is built wrong or the method of receiving bits is incorrect, it might best to verify them first. As it will be extremely unlikely that you get constantly incorrect data. PC keyboards and mice using the PS/2 protocol are so simple there should virtually be no errors or noise. Please post schematics and code, I am sure the problem is there. \$\endgroup\$
    – Justme
    Mar 5, 2023 at 9:47
  • \$\begingroup\$ I suspect it is the receiver block in my verilog code, I will post a link to the verilog, software routine. I get a parity but don't really do anything with it. One thing I wonder is I tried modifying a fifo receiver to use grey coding counter for the mouse fifo. I might not have needed to do that. Posting code shortly. \$\endgroup\$
    – Vahe
    Mar 5, 2023 at 12:24
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    \$\begingroup\$ People have been succesfully comnunicating PS/2 protocols with MCUs for almost 4 decades now. So indeed, it could be your Verilog code, or hardware that connects the 5 V bus to your likely non-5V FPGA/CPLD. \$\endgroup\$
    – Justme
    Mar 5, 2023 at 12:33
  • \$\begingroup\$ I use a level shifter and I have a 2 channel oscilloscope so I would be able to see the data / clock sent, I can compare if the signals are 1 to 1 matching. The thing is what do I look for, so far I do see one to one correspondence between the data signals in to out, I was thinking its the receiver FIFO that I changed to grey coding. The FPGA is 1.8V and the mouse is 5V externally powered as I use a level PCA9306 level shifter breakout pcb to translate to my FPGA. \$\endgroup\$
    – Vahe
    Mar 5, 2023 at 12:39

1 Answer 1

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The presented errors are occurring because when I get a new data I still check if the FIFO available to capture mouse packets is empty. And each empty check happens to read from the FIFO during empty check before reading for non empty values. That causes a case of double reading and consequently skipping over the next valid byte of data.

I modified the logic in the RTL code to check data was ready and assert a bit. Reading clears that bit.

Now I check for presence of data ready as opposed to FIFO not empty which resulted in consecutive unwanted reads thereby skipping bytes. This also means I need to remove the empty check on the FIFO read function and just read the data on the buffer. Once read then I inspect that data for presence of a ready flag meaning I have read new data. I also clear the data after reading so the value can reset to 0 after reading and clearing the ready flag.

I am in the process of debugging now but I think I should have a resolution soon to this long standing problem.

EDIT:

Increasing baud rate of my uart from 9600 to 19200 was done to exceed the bit rate of my ps/2 mouse which is at 12500 or 12.5KHz for 1 bit for baud. If I increase my baud rate I get more data faster but still misalignment occurs.

My uart baud is at 19200 for capturing an 8 bit + 1 bit stop. I set these parameters before but never looked them again on my terminal.

I even increased my processor frequency from 100MHz to 200MHz but did not think this might not fix the buffer overflow issue on UART, but it is starting to make sense now.

My UART fifo has been at 256 bytes and did not think to increase my output buffer to more than that, so I have now increased or doubled it to 512 bytes, I might double once more after that if 512 produces malformed results. I suspect these were the problems I overlooked in my initial attempts.

EDIT:

PS2 FIFO was replaced with a working module and UART baud rate was increased to 115200 bits/sec on both transmit/receive side Per comment underneath issue is resolved, see: Shared FIFO control module between UART, PS/2 protocol, UART is ok, PS/2 has issue locking on to packets during read

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  • \$\begingroup\$ A resolution was created to this issue: more details here electronics.stackexchange.com/a/659801/20332 \$\endgroup\$
    – Vahe
    Mar 22, 2023 at 5:09
  • \$\begingroup\$ It is also possible that you fix the software so it uses the value from the empty check instead of reading twice. \$\endgroup\$
    – user253751
    Mar 23, 2023 at 2:49
  • \$\begingroup\$ Good catch, that was a fix I did perform, but not the one that made the design work entirely. The issue presented was still not resolved until the FIFO was resolved, there was likely synchronization that needed to be done on the FIFO before this problem was completely fixed. Replacement of the module brought this issue to resolution. \$\endgroup\$
    – Vahe
    Mar 23, 2023 at 12:09

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