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This is my first 4-layer design and I can't easily find a clear answer to this question. I am designing a 4 layer PCB (signal-GND-pwr-signal), where regulated +12 and -12V power is supplied through a 3 pin connector (THT), along with the chassis GND connection.

In a two layer board, I would locate the board-wide bulk capacitors (220uF, aluminum electrolytic) adjacent to the main power connector, and route the power traces first from connector to capacitor, and fan out from there to the other Vcc pins of ICs, etc.

Since the main power connector is attached with through-holes, the board-wide copper pour for the power layer wants to attach to the incoming Vcc+, in addition to the positive pin of the bulk capacitor. (I also linked the capacitor and the connector directly by a fat trace on the top layer.)

Should I add a keep-out that prevents the connector from directly linking to the power plane? (Forcing the power plane to pull only through the THT pin for the bulk capacitor, which backhauls to the main power supply through the 2mm-wide top layer trace?) Or should I just allow both the power jack and the capacitor to connect to the power plane independently?

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    \$\begingroup\$ IMHO: In 95% of the cases it doesn't matter at all, you won't notice it in the performance, you won't notice looking at EM issues. In the other 5% were it matters, you won't face this problem, because you have to add some decoupling LC network or common mode filter to the power input. \$\endgroup\$
    – asdfex
    Mar 5, 2023 at 13:34

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A 220 μF bulk capacitor will have quite a poor high frequency response but, providing the tracks to it are thick-enough for the slower bulk of the current it is meant to "support", a couple of inches (or more) either way won't make a big difference.

Localized (and high-speed) decouplers close to the chips on the circuit board are what is important for reducing EMI and susceptibility so, providing you have this covered, the bulk capacitor position isn't going to make a big difference.

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    \$\begingroup\$ Thanks. Total board current draw is approx 150mA. (not a ton.) The board function is audio signal generation, so low noise < ~100 kHz matters more than fastest possible frequency response. There are 100nF mlcc's by each IC as well for local decoupling. I was led to believe that one should always have a bulk cap, and the bigger the better. 220u is what I have space for. Would it be better to exchange for something like a 22uF or 47uF solid tantalum? (I could fit a case C or D SMD in the same place.) \$\endgroup\$ Mar 5, 2023 at 18:37
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    \$\begingroup\$ @AaronKimball it depends where you power source is and, what you power source is. If generating an audio signal you might want to observe extra precautions that prevent the audio ground return signal sharing any path/copper with power 0 volts. This may call for a type of start-pointing in your ground plane. You might wish to do a spot of research on this: My answers on start-pointing for example. \$\endgroup\$
    – Andy aka
    Mar 5, 2023 at 18:47
  • \$\begingroup\$ Thank you, I will look at that. PSU is a chain: a "brick" that converts 120VAC to 12Vdc and then a board I made to generate -12VDC via a 2MHz Cuk converter, with 12" cable assy to this board. I plan to use a ferrite choke on the cable to eliminate wall power hum. Unfortunately I'm at the limit of what I can test before committing to pcb design; the lack of ground plane and relatively large circuit size means my breadboard is fine for testing core circuit correctness but the GND is bouncing everywhere and I can't test how different capacitor options would affect noise. \$\endgroup\$ Mar 5, 2023 at 18:58
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    \$\begingroup\$ Come back with a new question that specifically asks about the analogue 0 volts; show your layout in that question and relevant schematic parts. I should be able to contribute to answers given. A block diagram might be useful. It can be tricky with audio because the ear can pick-up stuff that your scope won't show. \$\endgroup\$
    – Andy aka
    Mar 5, 2023 at 19:01

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