# Are $V_{SS}$ and ground the same in integrated circuits?

As far as I'm aware, integrated circuits have two power rails, $$\V_{DD}\$$ and $$\V_{SS}\$$, where $$\V_{DD}\$$ is the drain voltage and $$\V_{SS}\$$ is the source voltage.

I've read that ground and $$\V_{SS}\$$ are considered the same in integrated circuits. Does that mean that $$\V_{SS}\$$ is always 0 V in integrated circuits?

In power electronics (tagged in the question) and analogue electronics, $$\V_{SS}\$$ can be a negative supply voltage hence, without further constraints, you cannot say that GND and $$\V_{SS}\$$ are the same. However, in modern digital circuits, they are almost exclusively the same node.

The link in your question is for NMOS, CMOS and TTL devices and $$\V_{SS}\$$ = 0 volts.

• Okay, so voltage rarely drops below zero in integrated circuits? Commented Mar 5, 2023 at 18:55
• I've noticed, on circuit-lab, that the voltage supply element can only be +/-. Should this be considered an abstraction when we're building digital circuits? Commented Mar 5, 2023 at 18:56
• @Connor I've rolled back your question to include power electronics because, I've made my answer based around that tag and, removing it after I have answered is not good practice and, even dilutes your question. Commented Mar 5, 2023 at 18:57

Strictly speaking, Vss is the voltage associated with the n-MOS source terminal (itself called Vs), and Vdd is associated with the drain (Vd). Vdd is generally taken as the more-positive of the two. GND doesn't enter into it - its relationship to Vdd/Vss is arbitrary.

Which raises a question. Why is Vdd regarded as more-positive than Vss, even though we observe in CMOS (and PMOS) logic the Vdd (higher) voltage connects to the p-MOS sources, not drains (that is, in PMOS Vs > Vd)? The fact that the world has adopted the Vdd-is-more-positive-than-Vss convention speaks more to the dominance of NMOS than anything else, despite PMOS logic having an early lead.

The Vdd/Vss bipolar equivalents are of course Vcc for collector and Vee for emitter. Again, conventionally, Vcc is taken to be more-positive than Vee. And again, this polarity would be for an NPN; for a PNP 'Vee' would be more positive than 'Vcc', but isn't even though for PNP has to have Ve > Vc to work.

And like Vdd/Vss, the relation to GND is arbitrary. ECL logic for example used GND as Vcc and -5.2V as Vee (-Vee).

Anyway, we go with the convention Vdd is more positive than Vss. When is Vss also GND? It is so in typical in NMOS and CMOS logic. In analog, mixed-signal or specialty driver circuits using FETs this doesn’t hold true. For example, a CMOS op-amp configured for bipolar operation could have -10V for Vss and +10V for Vdd.

Then there's the business of the FET substrate. As you may recall, FETs work based on their gate-to-substrate bias. In fact, a very useful structure, the transmission gate, connects substrate separately from source. This allows the FET to pass current in both directions without interference from that pesky body diode that's formed when source and substrate are connected together.

Some logic used a substrate voltage other than ground to achieve a better speed vs. leakage power trade off. A famous example is the Transmeta Crusoe 'LongRun' technology, more about that here: https://www.chipestimate.com/techtalk/techtalk_081007.html

In the most general sense, VDD and VSS can be whatever they need to be for your application, keeping in mind absolute Vdd-Vss limitations and your input levels. Internal to the IC, it only cares about the Vdd-Vss difference.

On several programs, we used standard, along with some custom, CMOS devices that were powered with Vdd = GND and Vss = -5 V to control some GaAs RF devices, which were powered from - 5V and GND.

On another, is was Vdd = +1 V and Vss = -2 V.

As Andy Aka said, for standard digital designs, it's usually Vdd = +5 V or +3.3 V and Vss = 0 V (or GND).

Finally, note that many FPGA's have several Vdds of differing levels, for the core logic and various IO banks.