# 8085 Memory address decoding with a NAND Gate

I have a problem for homework that has me stumped. Basically, what I'm given is 2 R/WMs, each 2048 bytes * 4. Connected to each of their CS pin is a NAND gate with pins A12-A15 connected from the 8085 microprocessor. The CS pins of both modules are in parallel with the gate. The RD and WR pins of each are connected top MEMR and MEMW. The pins of the modules are connected to A0-A10 of 8085 microprocessor. A11 is a don't care at logic 0 (I have no idea what this means).

The problem asks to identify the memory addresses. I've determined based on the NAND gate that the range would be from F000 to F7FF. This is where I'm stumped. First of all, that's a range of 800. Since that's in hex, I would think that gives only a range of 2048 bytes, which doesn't seem right. There's a total of 16k between the two modules, so something seems to be wrong.

I would think my problem is with the high order bits, 12-15 which go through the NAND. Could someone point me in the right direction? I've included a diagram of the problem below.

• If one of the address lines is truly a don't care (not connected to the memory or decoding logic), then memory will be accessible at two address ranges. Also don't forget that the 8085 has a multiplexed low address & data bus - perhaps that's already been handled upstream of this diagram. Commented Apr 16, 2013 at 4:35

## 2 Answers

I think you have it right. There are 16k bits, which is 2k bytes.

• Oh wwwooowww I did not even think of that..ok, that makes SO much more sense now! Commented Apr 16, 2013 at 3:58
• The two RAM chips are indeed a total of 16K bits. (2048 x 4) x 2 = 16384. However this is NOT the answer to the question. The question answer is supposed to be what addresses the RAMs will look addressable to the 8085. Your seeing it be from 0xF000->0xF7FF is only part of the correct answer. With A11 a don't care the 8085 will be able to "see" the RAM area at another address ranges as well. Your challenge now is to figure out what that other range would be. Commented Apr 16, 2013 at 5:18

Note that each chip is only 4 bits wide. The two of them operating in parallel — each connected to half of the data bus — give you 2K words of 8 bits each.