Ideas why this operational amplifier could have worse bias stability than anticipated

Question

Background

Below is the simplified schematic of an operational amplifier I tested. I left out compensation components, because the question is about the DC behavior only. The design has sufficient phase margin of ~70° and doesn't oscillate. This circuit is built tightly on a ~2x1 cm two-layer board all in SMD.

The left column is two current sources and a resistor for biasing the input differential cascode (middle column). The output stage is formed using a TL071H (CMOS version).

The bootstrapped cascode is an attempt to keep the input transistors always in the same environment. The goal of this design was to make both common-mode rejection ratio and input impedance "very high" in a voltage range leaving out the extremes close to the rails. Namely, based on extensive simulations (also using unmatched transistors!), I anticipated that input offset (\$V_\text{IN+}-V_\text{IN-}\$) should change only ~10 µV when going across most of the input voltage range.

^{simulate this circuit – Schematic created using CircuitLab}

Problem

What I observed, however, was a several mV change of the input offset voltage \$V_\text{IN+}-V_\text{IN-}\$, rather linearly across input common-mode voltage, i.e. while varying \$V_\text{IN+}\$.

Troubleshooting

I checked some voltages and found out a few things that worked well and others that deviated strongly from simulation:

• Node A stays firmly ~584 mV below the positive supply, so the top current source appears to be quite stable.
• The cascode bias voltage likewise is rather stable with only 1-2 mV of change across the input range.
• Node B changes strongly from 510 mV to 555 mV above the negative supply, indicating a strong change of the tail current. This was similarly stable to the top current source in the simulation. Q5 and Q6 are dual-packaged. Could it be that the heating of Q5 heats Q6 to cause such strong change? Could that also explain the comparatively low voltage drop? Using the thermal impedance of the package I estimate only 10 K max temp. rise even for the pass transistor Q5, so it sounds unlikely. Also, low input voltages should minimize the heat, but lead to the lowest voltage here of 510 mV, so opposite trend as expected for heating.
• Node C (TL071H bias) changes slightly from about 701 mV to 705 mV below the positive supply, which is in line with the previously observed varying tail current. But the surprising bit is that the offset between the two TL071H inputs changes by about 1.5 mV. I expected this to change only ~10 µV (output range divided by open-loop gain of TL071H).

So do you have any ideas what could give rise to the last two issues in particular?

Answer 1

Today, I modified the circuit based on a discussion I had with Ernesto G. in another question a while ago. Namely, I removed the current mirror (Q1 and Q2) and replaced it with two 470 Ω resistors, one in each branch. So essentially, there are now 570 Ω total resistance from each of the TL071H inputs to the positive supply. It is now only the TL071H that keeps the currents mirrored.

This change has resolved both issues. Now, the input offset voltage of the total circuit seems to be pretty stable with respect to the common-mode voltage. It still drifts based on temperature (and temperature is a function of common-mode voltage), but this is a slow change which is ultimately irrelevant for my application.

Therefore, my explanation what happened in the original circuit is: the bottom current sink wasn't able to sink its full design current. Instead, the TL071H seems to have looked for its own equilibrium in a state where the combined current out of both mirror sides was lower than the designed sink current.

The main drawback of that "fix" is that it reduces the gain of the input stage and therefore makes the noise of the output stage op-amp more relevant. This is reason, why I went for a current-mirror in the first place. To be able to use a noisy cheapo TL071 as the output op-amp.

The simulations never suggested a problem with that initial circuit idea, and to be honest, I still don't understand why the "fix" works. I will make this the topic of a separate question eventually, if I can't figure it out myself.

Answer 2

First thing is to clean solder flux.

The opamp is inside the feedback loop so its DC offset should be reduced by the high DC loop gain due to your transconductance input stage feeding its high impedance inputs. So I don't think the opamp is the culprit here. In order to rule it out, you can still try removing RL to avoid self-heating in the opamp output stage.

Next we have M1 and M2. There is the possibility that they are heated differently by nearby transistors, for example Q3 and Q4, maybe through the tracks. JFETs biased at the zero tempco point can give good stability versus ambient temperature, but the current required for this tends to be higher than you'd want.

Node B changes strongly from 510 mV to 555 mV above the negative supply, indicating a strong change of the tail current. This was similarly stable to the top current source in the simulation. Q5 and Q6 are dual-packaged. Could it be that the heating of Q5 heats Q6 to cause such strong change?

These cheap dual transistors (BCM847, etc) have two chips in the same package but they are not mounted on the same metal leadframe. So while both transistors can heat each other, heat conduction occurs through the plastic material and not metal, so it is inefficient and slow. This is a problem if you want to use it in a circuit where the two devices temperatures need to track. Heat sinking through the pins into PCB copper will be different for both transistors due to them being connected to different tracks, and that is enough to overwhelm the weak heat transmission through the plastic. To get the same temperature in both devices, dissipation needs to be kept very low.

Here are three measurements, done while heating one transistor in the dual and measuring Vbe in the other at constant current:

At first sight this may not seem useful for your problem, but... notice the delay between the two curves. There is a time lag as heat flows through the plastic into the other chip. DMMT3904 has lower lag because the chip is smaller (faster to heat) ; DMMT5551 has a larger chip thus a longer lag.

If you can probe offset versus time after a variation in common mode you should see it settling after a delay similar to the curves above. You can confirm the current source is the problem by wiring a pot (or a pin header) in parallel with R3 and forcing a change in tail current equivalent to what you're observing, but without changing the common mode. If this results in the same output offset drift as with the common mode voltage change, then the current source looks guilty.

If offset takes much longer to settle, suspect components heating each other through the board. Also blow on it to check what happens with ambient temperature changes.

There can also be leakage current in your compensation caps, depending on type.

Answer 3

Referring to Node B bullet

The cascode arrangement works by increasing the currents in both paths as the input voltage increases. And thus the tail current increases as well. By connecting the tail to the Widlar current source opposing actions result. The cascode needs current, but the current source tries to keep it constant. The Widlar current source is not especially good at that in my experience. So the tail wins out.

Your cascode requires the tail current to change so you should look at how to do that. I have a suggestion that I haven't tried, (but I will) that may work. See the inserted circuit diagram.

Qtail will divert the changing tail current from the current source which now has only the added base current from Qtail. So R3 can be increased to match the one in the other current source.

The currents entering the bases of Q3 and Q4 now return exactly the same quantity back to the current source maintaining symmetry.

^{simulate this circuit – Schematic created using CircuitLab}

Referring to the Node C bullet.

The common mode voltage range of OA1 extends to the positive rail. The common mode rejection (CMR) is successful only if the external circuitry is balanced to the midpoint supply voltage (Vref).

Think of the op-amp differential amplifier configuration. To maximize CMR the 4 external resistors must be matched.

The non-inverting input in your diagram has a much lower impedance to Vref than has the inverting input, thus providing an opportunity for common mode to differential conversion.

A Wilson current mirror may be a choice requiring one more transistor.

There may be other solutions that provide a better balance.