# Has anyone measured what a high-impedance pin looks like?

I understand that when an IC pin is in a high-impedance state, the pin is not connected to anything internal. It will be at the voltage to whatever it is being pulled from the outside.

I am just curious as to whether anyone has measured the value of voltage when the pin is in the high-impedance state.

Suppose, for example, an IC works at 5 V. A pin is in a high-impedance state at a particular instant. This pin is pulled up to 3.3 V since this signal is interfaced with an MCU. Now, let's remove the pull-up to 3.3 V on this pin. What would be the voltage reading? Just curious to understand this scenario.

• In the ideal case, it's undefined. Commented Mar 7, 2023 at 4:30
• it looks like a disconnected wire Commented Mar 7, 2023 at 5:20
• the meter you use to measure, with its finite input resistance of 1 or 10 megohms (usually) may well pull the pin to ground. Commented Mar 7, 2023 at 9:23
• @Hearth there is always a voltage whether you like it or not. "Undefined" means it can't be calculated from circuit theory. Commented Mar 7, 2023 at 12:19
• @user253751 Yes, the real world, which I am specifically excluding by saying "in the ideal case". Commented Mar 7, 2023 at 13:37

High impedance pins on an IC may be a varied range of voltage anywhere between the negative and positive supply rails.

Without outside interference the voltage level will be determined by what is connected to the pin circuit in the IC chip. In the case of some tri-stated output signal there are going to be OFF transistors that are present to pull this output high or low when the output is actually active. When in the off state these transistors will still have some leakage current, however small. The ratio of the leakage on the upper side and that on the lower side creates the effect of a high impedance voltage divider which ultimately determines the open circuit voltage on the open pin. Input pins can behave similarly due to leakage either due to that in the input protection diodes or to the input transistor gate leakages to the supply rails.

There are a number of external influences which can offset the open circuit voltage found on pins due to the internal leakages. These can include:

1. Probing with an oscilloscope which can change the node impedance on the IC pin in relation to the scope probe impedance which may be in the 1M, 10M or in some cases even 100M ohms. In many cases the probe impedance may be orders of magnitude less than the impedance of the open IC pin and totally override any native leakage voltage on the open pin.
2. Probing with a digital multimeter. See #1 above but the probe impedance may differ from that of an oscilloscope.
3. Circuit board traces or copper pours near the open IC pin may induce current into the high impedance pin and as a result change the pin voltage. The closer the adjacent copper is to the pin the more pronounced this effect can be. In addition to that the amount of current flowing through the adjacent copper can have a proportional amount of effect on an open pin.
4. Often open pins on ICs are connected to short traces which route out to a test point to facilitate board level testing in manufacturing. These short copper runs can intensify the effects mentioned in #3 above.
5. Stray capacitance and including the native capacitance of the pin of the IC package and the internal circuit node capacitance from on-chip will tend to hold charge to maintain the voltage level on an open pin for a relatively long period of time due to the very high impedance of the IC pin. The voltage on said capacitance may be set at the time the IC pin was last actively driven.

It is very important to keep in mind that there can be quite a variation of leakage current and impedance of pins from IC to IC of the same part number. So be careful not to draw conclusions by looking at a few parts from a particular manufacturing lot.

• Some chips allow input voltages to go beyond supply rails. Not all require the input voltages to be between supply and ground, not even if the supply was turned off so 0V. Commented Mar 7, 2023 at 6:53
• I would also add capacitive coupling with nearby mains lines. It is very likely that the high impedance pin will swing sinusoidally with an amplitude of a few volts (but little to no current) Commented Mar 7, 2023 at 15:55

The trouble with measurement is that you need to retrieve energy from the system being measured, in order to determine its state.

The very act of measuring is going to influence that state. One of the greatest challenges in experimental physics is to measure "gently". That is, to remove as little energy as possible from the system, so that your influence on the measured state remains negligible.

So, if you want to measure the potential of a "floating" node, your measurement equipment must draw/inject some current, and the aim is to make that current as small as possible.

A typical digital voltmeter has 10MΩ resistance between its probes, which is large, but not large enough. If you connected those probes between the floating node and ground, any current drawn through those 10MΩ would easily be sufficient to "pull down" the node's potential to ground also, and you would always measure zero. The act of connecting the voltmeter already invalidates the measurement.

So, if you want to measure that node's potential, you will require a voltmeter that draws negligible current, compared to whatever other current sources and sinks are connected to that node, a voltmeter with near infinite resistance between its probes. Such things do exist, but there are other considerations.

Consider a node that is "high impedance". Its resistance to anything else in the world, including the power supplies (say +5V and ground) is so high, that it might as well be infinite. Even if you have an infinite-resistance voltmeter, you have other problems to overcome.

If there are any electromagnetic (light, radio, x-ray, etc) sources in the vicinity, any photon has the potential to induce current in the metal of the node. This will cause its potential to fluctuate.

If there any sources of AC in the vicinity, such as mains power (120V or 240V AC), or a 1MHz digital square wave on a node nearby, these sources will be capacitively coupled to the node, causing the node's potential to fluctuate.

If that's not enough, the node still forms part of an extremely high impedance loop of conductors and components, and any magnetic field fluctuations inside that loop will induce currents that cause the node's potential to fluctuate.

In other words, the state of the node is in perpetual flux, and due to the high impedance between the node and everything else, even the tiniest external influence can produce a large change in potential with respect to everything else.

So, even if you were able to measure the potential without influencing it in any way, it's potential would be a changing value, a value subject to the presence of any potential changes near it or in the same room, any magnetic influences near it (caused by every current in every conductor within a few centimetres or metres), and every electromagnetic wave that happens to impinge upon it.

Even your own bodily presence near the node will increase the capacitance between the mains supply in your home and the node. You will also act as a giant antenna, reflecting and radiating electromagnetic "noise" to the node.

This is why a "high impedance input" should not be left unconnected, lest it oscillate wildly in potential, and have undesirable consequences to the systems "monitoring" its state.

The most significant "connection" that a high-impedance pin has to everything else is parasitic capacitance between that node and other conductors nearby. Generally, that's a few picofarads. Since it requires current to flow via these capacitances to change the potential differences across them, the potential at the node tends to be more stable than I may have insinuated above, but it is still very vulnerable to environmental conditions. Just bring your finger near to (but not touching) an unconnected CMOS inverter input, and watch that gate's output flap around wildly on an oscilloscope.

Typical output leakage currents are probably ~10nA at room temperature. The 1uA or even 10uA often shown as the limit in datasheets is grossly higher than the typical to account for elevated temperature and so as to not slow down testing. Leakage is primarily from the protection networks and from the 'off' MOSFETs, virtually none from the gates. Consider this TI datasheet:

Capacitance of a few pF means it will settle in a few milliseconds to some voltage Vx that lies between the power rails.

In other words there is a curve of pin current vs pin voltage and the current changes sign at some particular voltage Vx and above that current flows into the pin and below that current flows out of the pin.

We don't know what that voltage Vx is and it doesn't really matter since we are never going to deliberately float a pin like that.

Here is a datasheet for a chip that shows what was used then for a protection network. They're not necessarily this simple and AFAIK, protection networks are a rather important IP since they have to protect against substantial voltages to meet ESD standards.

A tristate I/O would likely combine features of both input and output protection. So you will have leakage of the low side diodes fighting the leakage of the high side diodes and the net amount comes in or out of the pin in steady state if the pin voltage is not at the voltage where the leakages exactly balance.

If one actually wanted to measure Vx, a simple way would be to use a very high impedance voltage follower and perhaps add some extremely low-leakage capacitance and definitely shielding to avoid picking up random noise. There are off-the-shelf cheapish op-amps that have fA input leakage (in ideal conditions) such as LMP7721 (low voltages only), LMC6001 so it doesn't take a $10,000 picoammeter, just maybe$10 +/- in parts and some skill and care.

Initially, upon removing the pull-up, the pin will be at 3.3V. The pair of reverse-biased protection diodes form a sort of voltage divider with a very high impedance due to their leakage. Absent any other influences or leakage paths, eventually the pin will decay to some midpoint self-bias value.

Note that any other features on the pin, such as a 3-state driver, or optional pull-up / pull-down, can also have their own leakages even when they’re not in use. These, too, will influence the pin self-bias voltage.

Environment will also influence the leakage, and thus self-bias. Leakage increases with temperature and with exposure to radiation. If the die is exposed, light will influence it too.

As to how to measure this self-bias voltage, a voltmeter with very high impedance (10G ohm) might do it.

A pico-ammeter used for measuring leakage current could also do it, by sampling the leakage as the other end of the meter is swept between Vdd and Vss. The minimum current reading would be at the pin’s self-bias point.

Another possibility is to use a Laser Voltage Probe (LVP), a non-contact instrument used in silicon failure analysis.

There will always be a certain amount of leakage current so the voltage is likely to drift up or down over time, essentially the residual capacitance of the IO circuit will hold the pin at its last-set voltage for a short time (possibly very short). If you try to measure the pin voltage using a DMM then you’ll likely see zero. As the meter has its own internal resistance, often quoted as 10k per ohm or whatever, which means when it’s on a 0-5V scale it will present a 50k resistance. On the other hand, if you connect the meter between +5V and the pin you’ll likely see 0V, telling you that the pin has pulled up to +5. With specialised equipment it’s possible to measure the voltage with much less load, but not zero load.