What is the reason of such conflicts? I read a book "Computer architecture" by Andrew Tanenbaum, but didn't understand the reasons may cause conflicts with memory with different timings, frequencies.
http://www.hardwaresecrets.com/article/Understanding-RAM-Timings/26/2 is worth a read on the subject.
Basically, DDR timings specify what the clock period should be and how many clock periods it takes for the data to travel to the RAM, select a row/column, read it out, and send it back. It's usually possible to send out another request before the first one is finished.
If you have two different sorts of RAM installed, the timing for one may not be suitable for another, and the controller will either not wait for the signal to come back, or sample it too late, or overwrite it by sending out another request too soon.
(There is usually a small EEPROM on the DIMMs which reports what the timing should be, using separate I2C lines).