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In the textbook picture, they use 5 NOT gates, repeatedly splitting the R input only to have it go into a different NOT gate. Are you allowed to put the input of R into a single NOT gate, and split the output twice? In this case, allowing you to have a total of 3 NOT gates, and 3 AND gates?
Having a logic output driving multiple logic input is normal. In ideal logic diagrams, a single logic output could drive an infinite amount of logic inputs, and on many occasions, a clock output will be used on all logic gates that need to run on that clock.
If a logic output could only drive one logic input, it would need a logic device which can internally split a logic signal into two, which again would be paradoxal - inside the chip you would still need to be able to split a logic signal into two.
In real world logic gates, depending on logic family, an output can drive somewhere around 4 to 20 inputs.
Buffers can be used to take a signal in and drive multiple inputs which allows to split a signal into multiple ones that can again drive multiple inputs. But each logic gate or buffer will also add a delay to the signal.
