Frequency multiplication with PLL circuit

Question

I am currently working on frequency multiplication with a PLL circuit.

I want to give it an input frequency of 10 kHz to 100 kHz and I want to get 160 kHz to 1.6 MHz from the VCO output. That's a multiplication factor of 16.

I found some ICs such as the CD74HC4046 and the MC14046B, but I can't arrange fmax-fmin. What I mean is, what range should I consider? 10 kHz to 1.6 MHz or 160 kHz to 1.6 MHz? Should I consider a low-pass filter cut-off frequency 1.6 MHz or 100 kHz? I found a CD74HC4046 SPICE file, but I don't know this file works well. I am still trying to find a good solution with the IC's datasheet. Can you give me some design tips about PLLs?

Answer 1

If you want an output frequency of 160 kHz to 1.6 MHz, then you need the VCO to cover that range. The CD74HC4046 part that you have in your question will cover that frequency range comfortably.

You then divide that by 16, to send 10 kHz to 100 kHz to your phase detector.

You don't need a low pass filter in the frequency signal paths.

You will need a loop filter in your PLL loop, which will need to be designed after you have chosen a loop bandwidth for your loop. A bandwidth much less than the minimum phase detector frequency is required, so less than 1 kHz.

If you have a high performance application and understand what you're doing, then there will be a correct choice of loop bandwidth. Otherwise, just pick a reasonable value in the few Hz to 1 kHz range. The lower the loop bandwidth, the longer the loop output will take to reach the correct frequency following a change.

There are plenty of application notes written around the 4046, showing how to compute loop filter components.

Answer 2

The standard application note is TI's SCHA0003 CMOS Phase-Locked-Loop Applications. However, for simple-language explanations and recommendations I suggest Don Lancaster's CMOS Cookbook, Chapter Seven. You should find sufficient information in these sources to answer your question.