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I'm working on a problem from an ETH Zurich course. They want you to build a transistor-level CMOS implementation of a XOR gate. My first attempt had floating nodes and other issues with untethered voltages.

My new attempt is the following:

schematic

simulate this circuit – Schematic created using CircuitLab

The answer given in the course is below:

ETH Zurich course XOR CMOS circuit

My implementation looks very similar to theirs. Except, when I simulate it in Circuit Lab, I don't get the correct voltage on the output. The only major difference I can see is that they have two inverters, one for A and one for B, directly after their inputs.

What am I missing? Why doesn't my implementation give the correct output voltages?

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    \$\begingroup\$ Having P-MOSFETs below the signal or N-MOSFETs above means using them in source follower mode, which always reduces the signal voltage at every gate. However I'm not sure if this is different when implemented on an IC due to the common substrate. \$\endgroup\$ Mar 9, 2023 at 15:58
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    \$\begingroup\$ other way around, the source follows the gate, +/- the threshold voltage. If you know BJTs (e.g. NPN transistors) It's analogous to emitter follower mode of a BJT. It's also called common drain (analogous to common collector). This mode can be used to amplify current but not voltage. \$\endgroup\$ Mar 9, 2023 at 16:02
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    \$\begingroup\$ For a proper sim, you should use 4-terminal MOSFETs with bodies tied to the supplies \$\endgroup\$
    – tobalt
    Mar 9, 2023 at 18:04
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    \$\begingroup\$ @Conner because that behaves different than the 3-terminal ones with source and body tied together. And when speaking about CMOS gates, the 4 terminal version is how they are made on the substrate. It might not make a difference for the truth table but probably for the dynamic behaivor. \$\endgroup\$
    – tobalt
    Mar 9, 2023 at 22:24
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    \$\begingroup\$ @tobalt Unfortunately, it's not something that looks like it will ever be added to CircuitLab. circuitlab.com/forums/feature-requests/topic/ufsz72dy/… \$\endgroup\$
    – Ste Kulov
    Mar 11, 2023 at 4:29

2 Answers 2

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The VTH for the MOSFETS that you have used is 4V. The source of M3 seems to be at 1.25V. As expected it will not go to 0V because the PMOS cannot pulldown to 0V. M5 transistor is OFF because it's VGS = 5V-1.25V = 3.75V which is lower than VTH. The gate of M9/M11 is hence floating and it's voltage is unpredictable. In this simulation, I could see it is 2.5V which is in between logic0 & logic1. The output is hence not matching your expectation.

In conclusion, this circuit also has floating nets because you have PMOS trying to pull a node to 0V which it can't do properly.

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  • \$\begingroup\$ Why can't it pull down to 0V properly? \$\endgroup\$
    – Connor
    Mar 9, 2023 at 17:24
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    \$\begingroup\$ @Connor, that is the operation of PMOS. Please read about the working. For PMOS to be ON, VGS>VTH. Here gate voltage = 0. The PMOS will be ON until the source is 4V. Below 4V, the PMOS is OFF and hence cannot pulldown the voltage anymore predictably. \$\endgroup\$
    – sai
    Mar 9, 2023 at 17:28
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Working solution:

schematic

simulate this circuit – Schematic created using CircuitLab

The source follower mode transistors were the issue, as stated by Sai.

Fixing that issue and placing PMOS transistors in connection with the drain, and NMOS transistors in connection with the source solved this.

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