1
\$\begingroup\$

I implemented an AND gate with Verilog, but the waveform keeps showing high-Z on the output (t1 and t2 are OK, but the others are not). I don't know what's wrong.

This is my code:

module ANDgate(A,B,Z);
  
  input A,B;
  output Z;
  assign Z = A & B;

endmodule

module ANDgate_tb();
  reg t1;
  reg t2;

  wire z1;

  ANDgate u1(A,B,Z);

  initial begin
     t1=0;
     t2=0;
  end

  always begin
     #5 t1=1;
     #5 t2=1;
     #5 t1=0;
     #5 t2=0;
  end

endmodule
\$\endgroup\$
1
  • 1
    \$\begingroup\$ Doesn't ANDgate u1(A,B,Z); need to be ANDgate u1(t1,t2,z1); instead? Also, I would be careful starting variable names with z in verilog since that's also a "number" like 0 and 1 are. \$\endgroup\$
    – Ste Kulov
    Mar 10, 2023 at 9:05

1 Answer 1

2
\$\begingroup\$

z1 is high-Z because you declared it as a wire in the testbench, but you did not drive it with anything. You should have connected it to the ANDgate u1 instance output.

Also, you need to connect t1 and t2 to the instance input ports because the input ports are undriven.

The signals A,B,Z in the testbench are implicitly-declared wires. You connected them to the instance, but they are not connected used anywhere else.

For example, change:

  ANDgate u1(A,B,Z);

to:

  ANDgate u1 (t1,t2,z1);

Now, you will see z1 toggle between 0 and 1 in your waveforms.

An even better way to make the port connections is:

ANDgate u1 (.A(t1), .B(t2), .Z(z1));

This clearly shows the name mapping between the testbench signals and the u1 instance port names.

See also: Verilog: How to instantiate a module

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.