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My circuit is designed for two to three 2.79Vf LEDs @ 3A (Cree XP-L on giant heatsink). It is powered from a 12VDC motorcycle battery.

Link to datasheet

The two vias in question are placed between the FB pin and Rsense in the layouts below.

I already sent my gerber files to JLCPCB, but I think I made a big mistake. I followed the datasheets layout for the demo-board (attached) and connected LED return (-VLED) into the FB loop using two vias. I now realize that those two little vias are likely insufficient for handling the return of the LEDs @ ~9V, 3A.

Are those vias (and the associated trace on bottom/blue layer) enough to handle that kind of power? It seems like it may be an insufficient ground.

ST Typical Circuit

ST Demo-Board Top Layer

ST Demo-Board Bottom Layer

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  • \$\begingroup\$ Depends on the size of the via. Use as many as you need to limit losses and voltage drop. \$\endgroup\$
    – winny
    Commented Mar 11, 2023 at 16:49
  • \$\begingroup\$ Thanks! I did use the same sizes (determined through scaling) of vias and trace as ST, so I hope I will be good. \$\endgroup\$
    – newguyjon
    Commented Mar 11, 2023 at 16:54
  • \$\begingroup\$ Don’t hope, measure, calculate and make sure. \$\endgroup\$
    – winny
    Commented Mar 11, 2023 at 16:56
  • \$\begingroup\$ It doesn't make sense that you put tracks underneath on what is the preferred layer for a ground plane and compromised both layers with additional vias. Where you can, route on top (for SMD components) and leave as much ground plane intact underneath. \$\endgroup\$
    – Andy aka
    Commented Mar 11, 2023 at 17:03
  • \$\begingroup\$ Yea, I thought the same, but I took that straight from the mfg datasheet. Too much blind faith on my end. \$\endgroup\$
    – newguyjon
    Commented Mar 11, 2023 at 18:52

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This should work.

A standard 0.6mm diameter via with a plating thickness of 20um allows 2.5A current flow.

For reducing the voltage drop and heat, you can decrease the resistance with a piece of copper wire, if the solder stop is not covering the via. You can can also scratch the copper surface free, put a 0.3 or 0.5mm copper wire through and apply some solder flux to the wire.

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  • \$\begingroup\$ Thanks! I read something similar while making the layout. I guess I should not have been so lazy and performed some conductor cross-sectional area calculations to determine trace vs. awg sizes. \$\endgroup\$
    – newguyjon
    Commented Mar 11, 2023 at 18:54
  • \$\begingroup\$ If I have the space, then I add some via at the end of the process to be on the save side. If there are signal lines, this could cause reflections, there you have to be very carefully, but for powerlines there is no problem with to low resistance. \$\endgroup\$
    – MikroPower
    Commented Mar 11, 2023 at 19:18

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