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Team, Thanks as ever for your wonderful support. Long time listener, first time caller.

I trying to make a low power active-high pulse (4-8sec RTC interrupt) when a switch is pulled to ground for up to 12hrs.

I followed this excellent example using a 2N3906 which forgoes a pull-up, incorporates a Simple RC time delay and created this on a breadboard.

schematic

simulate this circuit – Schematic created using CircuitLab

My question is; What is the best way to discharge the capacitor so that the pulse can be triggered again quickly?

Note: I do have the option of using the other contact on the SPDT switch but I'd rather not use it.

If there isn't a reasonable solution, can you recommend a circuit that would meet my low power active-high pulse requirements please?

EDIT: Q1 amended in schematic (good spot I don't know how that happened)

Use case is for a remote device:
1 - SW1 Open, system idle
2 - SW1 Closed, 4-8sec 3V3 INT pulse generated onto LDO ENable pin
3 - MCU powered by LDO
4 - MCU pulls up LDO Enable pin
5 - MCU does it's thing for 1min or so
6 - MCU goes to sleep, LDO ENable pin no longer pulled up and current passing through SW1 (SW1 still closed)
7 - Device inspected by human, SW1 Open, system idle

Logical representation of requirements is this: Logical representation of requirements

Is there a better way to discharge the cap when the switch is reset without using the other SPDT switch contact - maybe a diode?

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  • \$\begingroup\$ It's not clear what your circuit is supposed to do (Q1 is connected backwards), or what your specification is (up to 12 hours?) Is this what the circuit is supposed to do? Idle state, switch open, output is low. Switch closes to ground, output goes high (now, or in 4-8 seconds?). Switch stays at ground, output returns low after 4-8 seconds from going high. Switch stays closed, output stays low. Switch can stay low indefineitely, or only up to 12 hours? What happens after 12 hours? How long must switch stay closed or open for proper operation? \$\endgroup\$
    – Neil_UK
    Mar 12, 2023 at 10:43
  • \$\begingroup\$ Are you intentionally using Q1 in low-beta mode? \$\endgroup\$
    – Andy aka
    Mar 12, 2023 at 10:49
  • \$\begingroup\$ @Neil_UK Post edited with answers, good point on Q1 \$\endgroup\$ Mar 12, 2023 at 15:36
  • \$\begingroup\$ @Andyaka, do you mean that it was connected backwards (now corrected)? \$\endgroup\$ Mar 12, 2023 at 15:37

1 Answer 1

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This is my best effort so far:

schematic

simulate this circuit – Schematic created using CircuitLab

It uses two transistors, because I can't think of any other way to configure a single transistor as "open-collector", allowing control of the regulator's enable input to be shared between the timer and the MCU.

It also uses the switch as "push-to-break" (see a solution to that below), so that capacitor C1 is kept discharged while the switch is in its normally-closed state. To allow C1 to charge, switch SW1 is opened. When the switch closes again, C1 discharges very quickly, via R1.

After SW1 opens, and C1 has had enough time to charge to about 50% (which takes roughly 6s using the component values shown), Q1 switches off. Then R5 is allowed to pull Q2's base low, switching Q2 on and bringing the regulator's enable input high.

Q2 is performing three functions here. Firstly, it's inverting the logic output from Q1/R4. Secondly, it's sharpening up the transitions between high and low, for a cleaner enable signal to the regulator. Lastly, sitting high-side like that, it is allowing the output to be shared with the MCU. The regulator's enable input can be taken high either by Q2, or by the MCU pulling it high via D1.

When C1 is sufficiently charged, Q2 turns on, and the regulator's enable input goes high. At that point the regulator powers up the MCU, and the MCU brings its IO port output high. This state will maintain a high enable signal, even after Q2 switches off, and the MCU will remain powered until it sets its own output low.

If you insist on the switch being normally-open, and closing it should start the sequence by allowing C1 to charge, then another transistor is required:

schematic

simulate this circuit


UPDATE: With MOSFETs

Here's a solution using two MOSFETs, allowing us to keep current at about 10μA when the switch is open, and 20μA closed, until power is enabled:

schematic

simulate this circuit

The idea is to have M1 normally switched on, when switch SW1 is open, keeping C1 shorted and discharged. In this state M2 is off, with EN held low (0V) by R5.

When the switch is closed, M1 switches off, allowing C1 to charge, with the potential at G slowly descending. If the switch is opened again, M1 switches on again, almost immediately discharging C1.

If left long enough (SW1 is kept closed), eventually, G falls low enough to switch on M2, which causes EN to suddenly rise to +3.3V.

This is a plot of the switch closing then opening again (blue, 1V is SW1 closed, 0V is open), and the potential at G (orange), showing the slow charging (SW1 closed) and rapid discharge (SW1 open) of C1 when the switch is released:

enter image description here

Here's what happens to supply current and potential at EN:

enter image description here enter image description here

As you can see, supply current is 20μA or less prior to EN going high, at which point the regulator is enabled, and power is applied to the MCU and whatever else you have connected.

Importantly, the point at which M2 switches on is determined by its \$V_{GS(TH)}\$ parameter, which for the device in this simulation (BSS84) is 1.5V. That is, when G falls below \$3.3V - 1.5V = 1.8V\$, then M2 will switch on. Take care to choose a MOSFET with similar \$V_{GS(TH)}\$, in the range 1.5V to 2.5V, to obtain a switching threshold suitable for a 3.3V supply.

Your choice for M1 is less critical, but it still needs to have \$V_{GS(TH)} < 3V\$.

My use of a high-side P-channel MOSFET for M2 is deliberate. I require the EN signal to be pulled high by M2, but also by the MCU via D1, for a logical "OR" behaviour. A low-side N-channel device would not permit me to do that.


UPDATE #2: Resettable monostable

schematic

simulate this circuit

This time, the pulse begins as soon as switch SW1 is closed, and lasts about 6 seconds. If SW1 is opened again before the pulse has had time to finish, the pulse is immediately cut short. In the parlance of "monostable multivibrators" like this design, such behaviour is called "resettability".

M1 holds capacitor C1 discharged, while the switch is open. When the switch closes, M1 switches off, and allows C1 to slowly charge via R3 (and the negligible R4).

M2, M3 and R5 form a NOR gate. If either gate is high, the output EN is low. The only time EN can be high is when both SW1 is closed, and capacitor C1 is still charging.

Here's that behaviour plotted. In the top graph, orange is the switch state, and blue is the output pulse at EN. The bottom graph is current consumption throughout, which (aside from sub-millisecond spikes as the MOSFETs gates transition) shows that current is under 100μA during the pulse, and 20μA at other times.

enter image description here enter image description here

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  • \$\begingroup\$ This is great thanks @simon-fitch . Unfortunately with the normally-open config it busts my current budget <1mA. \$\endgroup\$ Mar 28, 2023 at 19:28
  • \$\begingroup\$ @Planestoner I can come up with something that does this with no current at all, until the switch is closed, but it will require CMOS logic gates and/or MOSFETs. Are you open to that, or do you want to stick with bipolar transistors? \$\endgroup\$ Mar 29, 2023 at 3:07
  • \$\begingroup\$ @Planestoner I made a MOSFET-based version, appended to my answer. \$\endgroup\$ Mar 29, 2023 at 6:34
  • \$\begingroup\$ @Planestoner I do realise that this design doesn't permit the MCU to cut its own power while SW1 is closed. That's another issue, and I am thinking about it. \$\endgroup\$ Mar 29, 2023 at 6:42
  • \$\begingroup\$ Sincere thanks @simon-fitch. I'm concerned that my explanation wasn't clear as I ran your simulation which may not fully meet the requirements. As a use case, imagine a door is opened which closes a switch. When the switch closes a 4-8sec INT pulse is generated. During this pulse current is drawn and then it drops to near zero until the switch opens and re-closes. The door can remain open for anywhere between 60secs and 12hrs. Ideally as soon as the door is closed I'd like the system to be reset almost instantly. \$\endgroup\$ Mar 29, 2023 at 20:00

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