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I am working on a PLL design. I am at the research stage now. I am confused about the PLL input frequency range.

This frequency has to remain constant. If this input frequency stays constant, how can we change the output frequency? I want a variable frequency range at the input (10 kHz to 100 kHz), so my output will be 160 kHz to 1.6 MHz (x16 multiplication factor). Is it possible to make this kind of design?

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  • \$\begingroup\$ Since output frequency = N X Fref, you can change N or Fref to change output frequency. However, for each case, you need to ensure that the loop is stable and also ensure that the VCO can give the required output frequency. Your question is not 100% clear to me. Why do you say that the input frequency has to remain constant? Note that there are other parameters of a PLL like startup time, phase noise and reference spur. I'm assuming you are not worried about them for now. \$\endgroup\$
    – sai
    Commented Mar 14, 2023 at 7:31
  • \$\begingroup\$ Hi @sai thank you for your answer. I did not say input frequency remain constant. I said Has input frequency to be remain constant? Is this mandotory? And you said you can input frequency, ı got my answer. Of course ı am worried about these issues but my priorities is handling fundamental issues. Btw do you know any design notes that we can change input frequency except Texas SCHA003B? \$\endgroup\$ Commented Mar 14, 2023 at 7:43
  • \$\begingroup\$ My answer was a generic one. I have not worked with discrete PLL ICs. When using discrete PLL ICs, you can better follow what is given in their respective app notes. \$\endgroup\$
    – sai
    Commented Mar 14, 2023 at 8:03
  • \$\begingroup\$ Thank you @sai. \$\endgroup\$ Commented Mar 14, 2023 at 8:20
  • \$\begingroup\$ What loop bandwidth is required for your loop? Do you even understand the question? A related question is, how fast must the output frequency respond to a change in input frequency? \$\endgroup\$
    – Neil_UK
    Commented Mar 14, 2023 at 8:47

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This frequency has to remain constant. ???

You happen to have found an example where they choose this to be true, presumably from some application note you don't credit. It's a common way to use a DPLL, have a variable multiplication factor from some fixed, low noise, often crystal-derived reference.

However, the input reference frequency to your loop can have any value. 10 kHz to 100 kHz? No problem. In that diagram, replace '/N counter' with '/16 counter' (being pedantic should really be '/16 divider', and write 'minimum 10 kHz' next to Fref.

The stability of the loop depends on, amongst other things, the latency of your phase detector, which for a digital phase detector is proportional to the period of the reference frequency, worst at the minimum frequency. Normally if you have a loop bandwidth well below the lowest reference frequency, say 100 Hz for a 10 kHz Fref.min, then you can neglect this latency. If you want to push the loop bandwidth closer to Fref.min, say 1 kHz or more, then your loop filter must have less phase shift than a typical design would use, to accommodate this latency. If the loop is stable at the lowest frequency, you'll be fine at all higher frequencies.

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  • \$\begingroup\$ Hey, @Neil_UK, CD74HC4046 is suitable for this design? \$\endgroup\$ Commented Mar 14, 2023 at 14:37
  • \$\begingroup\$ @natarajmarble 4046 is suitable, as I answered to your other question. Do you understand the concept of loop bandwidth? That question needs to be answered before it's possible to pitch any reply to your questions. \$\endgroup\$
    – Neil_UK
    Commented Mar 14, 2023 at 15:17

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