I am working on a PLL design. I am at the research stage now. I am confused about the PLL input frequency range.

This frequency has to remain constant. If this input frequency stays constant, how can we change the output frequency? I want a variable frequency range at the input (10 kHz to 100 kHz), so my output will be 160 kHz to 1.6 MHz (x16 multiplication factor). Is it possible to make this kind of design?

• Since output frequency = N X Fref, you can change N or Fref to change output frequency. However, for each case, you need to ensure that the loop is stable and also ensure that the VCO can give the required output frequency. Your question is not 100% clear to me. Why do you say that the input frequency has to remain constant? Note that there are other parameters of a PLL like startup time, phase noise and reference spur. I'm assuming you are not worried about them for now.
– sai
Commented Mar 14, 2023 at 7:31
• Hi @sai thank you for your answer. I did not say input frequency remain constant. I said Has input frequency to be remain constant? Is this mandotory? And you said you can input frequency, ı got my answer. Of course ı am worried about these issues but my priorities is handling fundamental issues. Btw do you know any design notes that we can change input frequency except Texas SCHA003B? Commented Mar 14, 2023 at 7:43
• My answer was a generic one. I have not worked with discrete PLL ICs. When using discrete PLL ICs, you can better follow what is given in their respective app notes.
– sai
Commented Mar 14, 2023 at 8:03
• Thank you @sai. Commented Mar 14, 2023 at 8:20
• What loop bandwidth is required for your loop? Do you even understand the question? A related question is, how fast must the output frequency respond to a change in input frequency? Commented Mar 14, 2023 at 8:47