Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It only takes a minute to sign up.
Sign up to join this community
I am working on a PLL design. I am at the research stage now. I am confused about the PLL input frequency range.
This frequency has to remain constant. If this input frequency stays constant, how can we change the output frequency? I want a variable frequency range at the input (10 kHz to 100 kHz), so my output will be 160 kHz to 1.6 MHz (x16 multiplication factor). Is it possible to make this kind of design?
This frequency has to remain constant. ???
You happen to have found an example where they choose this to be true, presumably from some application note you don't credit. It's a common way to use a DPLL, have a variable multiplication factor from some fixed, low noise, often crystal-derived reference.
However, the input reference frequency to your loop can have any value. 10 kHz to 100 kHz? No problem. In that diagram, replace '/N counter' with '/16 counter' (being pedantic should really be '/16 divider', and write 'minimum 10 kHz' next to Fref.
The stability of the loop depends on, amongst other things, the latency of your phase detector, which for a digital phase detector is proportional to the period of the reference frequency, worst at the minimum frequency. Normally if you have a loop bandwidth well below the lowest reference frequency, say 100 Hz for a 10 kHz Fref.min, then you can neglect this latency. If you want to push the loop bandwidth closer to Fref.min, say 1 kHz or more, then your loop filter must have less phase shift than a typical design would use, to accommodate this latency. If the loop is stable at the lowest frequency, you'll be fine at all higher frequencies.
