I designed a couple of bandpasses for an audio project, 15 in total. Only 3 of those 15 bandpasses show a passband gain which match my calculations and simulations.

What could cause this gain mismatch?

Before actually putting them on a PCB, I verified my calculated values with this calculator: http://sim.okawa-denshi.jp/en/OPttool.php and ran some worst case simulations (taking into account the tolerances of resistors and caps) in LTSpice. All bandpasses use the exact same PCB layout.

One of those bandpasses:

calculated center frequency : \$f_c = 104.67 Hz\$ passband gain: \$g = +6.7 dB\$ and quality factor: \$ q = 9.6\$

measured passband gain: \$g = +3.0 dB \$

bandpass schematic

Output of the worst case simulation with 1% resistor tolerance and 10% cap tolerance, using the TL074 model provided by TI. Lowest simulated passband gain is \$ +5.6 dB \$ worst case simulation

My thoughts so far:

  • just based on its specs, the TL074 should be more than capable of providing the desired passband gain
  • the influence of the tolerances of the passives was covered the worst case simulation and don't match the measured gains
  • I could lower the gain in the simulation to the measured value by adding a small capacitor (\$ \sim10 pF \$) from opamp output to negative input. this would model the effect of parasitic capacitance. but it doesn't work for all bandpasses. The example above would require a 100 pF capacitor to reach the measured gain, which seems unrealistic.

It seems like there must be an obvious solution to this puzzle, I just don't see it and would be happy about any input.

additional simulations:

Simulations with extreme values and adjusted for correct center frequency, simulated gain well above measured results:

simulation with extreme values 1:

simulation with extreme values 1

simulation with extreme values 2:

simulation with extreme values 2

simulation with trimmer adjusted to desired center frequency:

simulation with adjusted trimmer

  • \$\begingroup\$ Why are there three passbands shown in your spectrum? What is node 002? How accurately do you have to set the pot? What tolerance does this have? What wiper resistance does it have? \$\endgroup\$
    – Andy aka
    Mar 14, 2023 at 11:46
  • \$\begingroup\$ - the three passbands are a result of the cap tolerances, on the board those can be compensated with the pot - node 002 is the output of the opamp - the pot is used to trim the center frequency to the desired value - the pot has a tolerance of 10% and a wiper resistance of 2Ohm \$\endgroup\$
    – infra
    Mar 14, 2023 at 11:57
  • \$\begingroup\$ Have you simulated an intentionally worst-case-tolerance capacitor that is frequency centralized by adjusting RV901? And then see how much that might affect the passband gain range. I know that Q is affected significantly by R903 and RV901 so, that might be the problem. \$\endgroup\$
    – Andy aka
    Mar 14, 2023 at 12:01
  • \$\begingroup\$ but isn't the gain in the passband defined just by R907 and R901? when evaluating the filters on the pcb, i would apply the desired centre frequency and adjust the trimmer until i see the maximum amplitude at the output. by that i should get the correct passband gain, even if the Q wasn't right, no? \$\endgroup\$
    – infra
    Mar 14, 2023 at 12:07
  • 1
    \$\begingroup\$ No, the passband gain will be affected if (say) C905 reduces by 10% and RV901 is adjusted to compensate for the frequency shift. I reckon it will lower passband gain by about 0.47 dB. Then if you adjust all values to their extremes..... \$\endgroup\$
    – Andy aka
    Mar 14, 2023 at 12:33

3 Answers 3


For my opinion, the feedback resistor (436 kOhms) is too large - in comparison with the neglected input resistance of the opamp.

Remember: For all calculations based on ideal opamp all resistors should be much larger than the (neglected) opamps output impedance and - at the same time - much smaller than the (neglected) input impedance of the opamp.

EDIT: On the other hand, the results are not surprising. The midband gain is (nomenclature as in the 1st figure):

$$A_m=\left[\frac{C_{907}}{(C_{907}+C_{905}}\right] \cdot \frac{R_{907}}{R_{901}}.$$

For two equal capacitors and 10% capacitor tolerances, the worst case deviation of the first factor (nominal 0.5) is ≈1.8 dB.

  • \$\begingroup\$ Thanks for editing. \$\endgroup\$
    – LvW
    Mar 14, 2023 at 17:42
  • \$\begingroup\$ The TL074 datasheet specifies a differential input impedance of \$ 100 M\Omega \$, so this should be large enough to use a feedback resistor in the range of some hundreds \$k\Omega\$, no? \$\endgroup\$
    – infra
    Mar 15, 2023 at 8:35
  • \$\begingroup\$ the gain deviation caused by the capacitor tolerance should be covered by the worst case simulations. in the example above this resulted in a minimum gain of \$ +5.6 dB\$, the measured gain is only \$ +3.0 dB\$, though. \$\endgroup\$
    – infra
    Mar 15, 2023 at 8:38
  • \$\begingroup\$ @infra, which graph shows a gain of 3dB? \$\endgroup\$
    – LvW
    Mar 15, 2023 at 9:24
  • \$\begingroup\$ none, unfortunately :) this is the gain i measure with the real circuit on pcb and breadboard. \$\endgroup\$
    – infra
    Mar 15, 2023 at 9:26

Have you taken into account parasitic L/C/R from your pcb traces? If the PCB is to thin then their will be more capacitance to ground, if your traces are thicker and longer than their will be more inductance and if they are thinner and longer, they will have more resistance. Try taking this into account in your simulation as well. Also as far as I know, LTSpice doesn't simulate tolerances despite that being in the dialog box. I am probably wrong about this however. Please edit your post to add your PCB layout.

  • 3
    \$\begingroup\$ Thinner traces produce less capacitance and more inductance. \$\endgroup\$
    – Andy aka
    Mar 14, 2023 at 13:12
  • \$\begingroup\$ I am talking about the board thickness itself. If the board is 1mm thick than the capacitance to the other side of the board (gnd) will be much more than a board that is 5mm thick. \$\endgroup\$ Mar 14, 2023 at 13:17
  • \$\begingroup\$ yes, i ran multiple simulations with added capacitance. additional capacitance to ground in a reasonable range (few pF) at opamp inputs wouldn't result in a gain reduction in passband. i could lower the gain by adding a capacitor from opamp output to inverting input, parallel to the feedback resistor. some circuits, like the example above, would require 100pF to lower the gain to the measured value. this seems unreasonable to be caused by the pcb. also circuits on breadboard show similar behavior, which somehow indicated that board geometry isn't the root cause. \$\endgroup\$
    – infra
    Mar 14, 2023 at 13:17
  • \$\begingroup\$ Than I am completely stumped. I am sorry but I can't help any further. \$\endgroup\$ Mar 14, 2023 at 13:19
  • \$\begingroup\$ @catsarethebest you said this: if your traces are thicker and longer than their will be more inductance <-- not true because thicker traces lower inductance. \$\endgroup\$
    – Andy aka
    Mar 14, 2023 at 13:26

To model this, use a Monte Carlo simulation with the value of RV901 calculated to bring the frequency to where it should be. I.e. RV901 must be a function of other resistance and capacitance values to reflect what you're actually doing when tuning the circuit. And if we indeed do this, then the simulation foresees your results :)

It is normal and expected to tune both the frequency and center frequency gain in practical filter circuits. So you'd want another buffer stage with an RV to adjust the gain to what's needed. There's no way around it, in fact. Tuning the center frequency does not tune the gain at that frequency! - if anything, it'll mess the gain up, since your circuit is tuned with a resistor that controls the DC gain.

If I was putting this circuit together, I'd rescale the capacitors to 100nF ±1% C0G (they are much cheaper than 68pF ±1% C0G), and add a fixed 15pF ±1% C0G capacitor across R907 for stability. Resistors should be ±0.5%. R905 won't improve anything much and I'd leave it off. If you do that, the gain range may just be good enough to leave it be without trimming, since the RV901 trim range will be >5x smaller than it was before.

Also, you'll really want to run this under a network analyzer (the ones built into modern oscilloscopes are good enough) and see what happens when you bring anything conductive near to the circuit. It may need a shield for robustness.

  • \$\begingroup\$ added the requested simulation. minimum gain is similar to previous worst case simulation and still way above measured results. this is also kind of expected, as the passband gain isn't affected by the trimmer value, see answer above. \$\endgroup\$
    – infra
    Mar 15, 2023 at 9:18

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