# Input common-mode offset voltage ranges of op-amp

I'm using an MCP6V81 op-amp.

While trying to understand, I see that the output of the op-amp can't be greater than Vdd and less than Vss. If that's the case, could someone clarify how the common-mode input voltage ranges can be greater than Vdd by 0.3 V and lesser than Vss by 0.2 V? How does the op-amp accept these inputs when the supply limits are exceeded? These values are mentioned in the electrical characteristics table of the datasheet.

From my understanding, the common-mode input voltage of an op-amp is the voltage that is applied to the input terminals of the op-amp. From the above datasheet, it is Vdd + 0.3 V and Vss - 0.2 V.

So, if my power supply terminals are +2 V and -2 V, then how should I give my inputs?

• @Andyaka accepted the answer Mar 20 at 10:08

could someone clarify how the common-mode input voltage ranges can be greater than Vdd by 0.3 V and lesser than Vss by 0.2 V? How does the op-amp accept these inputs when the supply limits are exceeded?

Basic differential amplifiers using NPN

A simple differential input amplifier forms the basis of most (if not all) op-amp input stages. A drawback of this arrangement (when using NPN transistors), is that if the input voltage falls below a certain level (about 2 volts above the negative rail), the NPN transistors can no longer be adequately base-biased and, they don't function.

On the other hand, you can raise the bases of the differential pair to the positive supply voltage and, the input stage operates correctly. Raising the inputs higher than the positive supply voltage is also possible to a certain degree. A simple NPN differential input amplifier: -

Image from Differential Amplifier using Transistors.

However, as the input rises above the positive rail, you start to forward bias the base-collector region and this results in signal inversion; the base directly couples to the collector resistor (via the now forward biased base-collector region) and what was an inverting stage becomes a non-usable non-inverting stage.

So, an NPN differential amplifier can work providing its inputs are in the range of approximately 2 volts above the negative rail to slightly more than the positive rail.

Basic differential amplifiers using PNP

If we then considered a PNP differential input stage (used in well-known devices as the LM324), the opposite is true; the inputs can range from about 2 volts below the positive rail to slightly below the negative rail. LM324: -

Hint - what we would really like is to be able to combine both NPN and PNP differential transistors so that inputs can range from slightly below the negative rail to slightly above the positive rail.

However, this desirable combination isn't usually implemented using NPN or PNP differential input stages but, it is done with MOSFET input stages on many modern op-amp devices.

Rail-to-rail differential amplifiers using MOSFETs

Here's a typical MOSFET input example from the TLV379 data sheet: -

It's quite a bit more complicated than a simple BJT differential amplifier but, hopefully you can see how it works.

if my power supply terminals are +2 V and -2 V, then how should I give my inputs?

The maximum input range is -2.2 volts to +2.3 volts (for the device that you specified).

Consider this simple amplifier. If the Vth of the NMOS is much higher than Vgs of the PMOS, you can connect the inputs to a voltage higher than VDD eventhough the output cannot go higher than VDD. In this example, VDS of the input pair is 5.4-VIN and if say VDSAT is 0.1V then, VIN can be 5.3V max and all devices will be in saturation. Note that VIN is higher than VDD by 0.3V

Normally all inputs have ESD diodes to VDD and VSS. So, the limit for the input voltage will be limited to VDD+0.3 because the limitation is coming from the ESD diodes.

However, keep the common mode voltage between VDD & VSS because in the specification sheet, you can see that at high temperatures, VCMH-VDD and VCML-VSS become almost 0. (figure 2-19)

• Thank you for your answer. Could you please explain how you are comparing the Vth of NMOS and the Vgs of the PMOS? Both are supplied by the same power line? Any example values with the above diagram please? Mar 15 at 10:45
• @Newbie, please checkout this video and see if it helps. youtube.com/watch?v=D60-68JcQD0
– sai
Mar 15 at 10:53
• @Newbie, I also added some numbers in the diagram for your understanding
– sai
Mar 15 at 11:11

The opamp's output is constrained by the power supply potentials, so you'll never get an output that falls outside that range. That's written $$\-2V < V_{OUT} < +2V\$$, in your example case.

This has nothing to do with what input potentials the device can tolerate, because the circuitry that deals with inputs is physically different from the circuitry that produces the output. They are separate "systems" within the IC, with a lot of other "systems" in between.

Acceptable input potentials are defined by the circuitry that handles them, and the range may or may not be different from the range of possible output potentials. There are good reasons to want the inputs to tolerate anything the output can produce, though; take a look at the voltage follower:

simulate this circuit – Schematic created using CircuitLab

This is a very common configuration, used to "buffer" some input signal, to provide a strong copy of it that's able to drive loads which require more current than the original source has to offer.

The output produced by the op-amp here is fed directly back to one of its own inputs. Imagine if this device has an output that can have any value between −2V and +2V, but its inputs were only able to tolerate, or behave predictably with, inputs ranging from −1.5V to +1.5V. This op-amp could give itself a hernia.

In the case of your device, the MCP6V81, with supplies of $$\V_{DD} = +2V\$$ and $$\V_{SS} = -2V\$$, the output is able to reach almost +2V or almost −2V (within a few millivolts), and can swing around happily between those extremes.

For its inputs, the datasheet tells you that you can apply potentials in the range $$\V_{SS}-0.2\$$ to $$\V_{DD}+0.3\$$, which with supplies of ±2V would mean that any potential, between −2.2V and +2.3V, at either input, is acceptable.

By "acceptable" I mean that the device won't be damaged, and the function of the op-amp will be as you expect. The relationship between inputs (P and Q) and output (OUT) will conform closely to:

$$V_{OUT} = A(V_P - V_Q)$$

where $$\A\$$ is some huge number representing the open-loop gain of the op-amp.

In other words, as long as your input voltages are within the allowable range −2.2V and +2.3V, and you don't do anything stupid with the output, that relationship will be obeyed. I won't go into what constitutes "stupid", except to say it includes anything connected to the output that prevents the op-amp from applying its own choice of potential there.

What happens when input potentials fall outside that acceptable range? Well, two things spring to mind. The first is that the op-amp may or may not have diodes in place which prevent you doing exactly that. Many devices have diodes inside the IC, like this:

If they are present, their primary purpose is to protect the whole op-amp from ESD, electrostatic discharge, but they have the side effect of also preventing you, the user, from explicitly applying potentials further than 0.3V or so beyond the power supply rails. Under such circumstances, they become highly conductive, bypassing current to the power supply rather than through their own sensitive circuitry.

If you do try to impose potentials significantly outside the power supply range, either so much current will flow that you destroy these diodes, swiftly followed by the destruction of everything else in the IC, or current demand will be so great that the source of the input signal is unable to maintain this over-voltage condition.

The other thing that can happen if inputs stray outside the acceptable range (assuming you don't damage anything in doing so), is that the op-amp's internal biasing is disturbed, and it enters a state in which it is no longer able able to promise that $$\ V_{OUT} = A(V_P - V_Q) \$$. Consequences vary from device to device. Older devices would suddenly swing their output from one extreme to the other, a phenomenon called "phase inversion", while modern devices tend to be better behaved.

As for your question, regarding the MCP6V81, with supplies of ±2V, you must never apply potentials to either input that are greater than +2.3V, or more negative than −2.2V. I don't know what will happen if you do, but I do know it will not be good.

Maybe you are asking "how is it possible to apply a potential higher than +2.3V, or lower than −2.2V, since the circuit's power supply is +2V and −2V?" Well, off course you can. Many systems have multiple supplies. Just because the supply you give this particular op-amp is ±2V, doesn't mean there aren't other sub-systems in the same circuit that use different supplies, and any one of them can produce signals that fall outside the range −2.2V to +2.3V.

And yes, if you are connecting the output of one such sub-system (with its own supplies) to an input of your op-amp, you'd better be sure that it's constrained to be within that op-amp's limits, otherwise at worst you break something, or at best you invoke some undefined op-amp behavior.