# Question

Hi there,

So in the following image taken from Razavi, the part highlighted confuses me. He states the sum of all the overdrive voltages in each cascode branch is equal to 1.5V. Now, is this 1.5V because that's Vdd/2, or is that 1.5V because it states previously that node X and Y must swing 1.5V p2p?

For example, if we only were require the output voltage to swing between 1V-2V, how would that affect the equation involving $$\V_{OD}\$$?

Furthermore, if instead we wanted have the output swing from 2V-3V, we'd best (I assume) bias it so that the common-mode output voltage is 2.5V and have there be a 0.5V p2p swing each way. In that case, what would be the restriction on the overdrive voltage in the same way that it is stated below?

# Circuit

The sum of the overdrives must be 1.5V because peak-peak differential output needed is 3V i.e., single-ended peak-peak at X or Y is 1.5Vpp.

VDD minus the single-ended peak-peak swing is the budget available for the overdrives provided the output common mode is set at the right value i.e., mid-point of VDD-VOD7-VOD5 & VOD9+VOD1+VOD3

The moment you constrain the common mode voltage of the output, we need to have additional constraints.

If you say that the single ended output (X or Y) needs to swing between 1-2V, then, VOD9+VOD1+VOD3 < 1V &
VOD7+VOD5 <1V (i.e., VDD-2V).

If you say that the single ended output (X or Y) needs to swing between 2-3V, then, VOD9+VOD1+VOD3 < 2V &
VOD7+VOD5 <0V (i.e., VDD-3V). So, this is not possible

In all this discussion, we make a fundamental assumption that you bias the cascode gate at a voltage such that the mirror transistor's VDS is equal to the over-drive voltage.

• Thank you for the answer, this clears things up! Commented Mar 16, 2023 at 13:03