1
\$\begingroup\$

I'm still pretty new to Verilog and all and could use some help completing/fixing my code for this problem. I have made the state diagram, state table/assignment, minimized the equation, and even have some of the Verilog done, but I'm just not too good at understanding Verilog.

Here's the prompt:

Derive a sequential circuit with one input (w) and one output (z) using D flip flops that detects an input sequence of 101. Use a Moore model, and show all of your work including the state machine, state table, state assignment, state assignment table, and the final circuit.

PS, I also don't know how to fully draw the circuit. But other than that, here's the progress I've made:

(I don't have a high enough rep to embed images if someone can do that for me, thanks)

State Diagram:

enter image description here

State Table, Assignment, and Minimal equation

enter image description here

Besides the circuit diagram, I have the first part done. Now I have to implement this as a Verilog program.. even though I'm not quite sure where I'm going with it. I've looked at some examples and this is what I've got so far:

Verilog code so far

module my_circ(Clock, Resetn, w, z);

    input Clock, Resetn, w;
    output z;
    reg [3:1] y2, y1, Y2, Y1 //not sure about this line.. probably throws the rest off
    parameter [3:1] A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;

    always @(w,y2,y1)
        case (y2)
            A: if (w)  Y2 = 0;
                       Y1 = 1;
               else    Y2 = 0;
                       Y1 = 0;
            B: if (w)  Y2 = 0;
                       Y1 = 1;

    /////////// I don't think this is right at all :(
            default:    Y1 = ...

    always @(negedge Resetn, posedge Clock)
        if (Resetn == 0) //something :/
        else //something else :/

    assign z = (...); //something :/

endmodule

After trying to write that Verilog, I realize I'm just about clueless when it comes to implementing this :( I tried following different examples but all of the ones I can find use 3 states instead of 4 like this one. I think I should have multiple cases? And ugh idk where to set which variables and what to set them to.

Any advice will help me. Thanks.

\$\endgroup\$
0
\$\begingroup\$

Actually, the structure of your verilog looks just fine. It's the details that are wrong, in a lot of places. Here are some:

reg [3:1] y2, y1, Y2, Y1

Yes, the missing semicolon throws the compiler off. More to the point, [3:1] tells it that each of these regs is three bits wide, but they're only one bit wide in the planning. Traditionally we use 0 for the least significant bit (such that the binary interpretation has weight 2^n at bit n). The parameter line would thus be [1:0], as it is you extend it to three bits wide.

always @(w,y2,y1)
always @(negedge Resetn, posedge Clock)

The sensitivity list is separated by or, not comma.

    case (y2)
        A: if (w)  Y2 = 0;
                   Y1 = 1;
           else    Y2 = 0;
                   Y1 = 0;

y2 in this case statement only matches one bit in your planning (three in the code, but that made less sense). You can concatenate bits using {y2,y1}; in fact, extending the case to case ({y2,y1,w}) will let you use case matches like {A,1'b0}: and remove the if statements entirely.

Secondly, you are trying to manage groups of statements (both assignments to Y2 and Y1) with if; doing so requires enclosing them with begin and end. Alternatively, you could make a wider assignment such as {Y2,Y1} <= B;, which ends up more readable as it can use your named states.

Thirdly, assignment using = can cause some confusion (it acts more like sequential languages, while <= doesn't modify the meaning of a reg within your always). In this case, it is fine as the block is fully combinatorial and does not depend on its own outputs.

Finally (for the case section), you can simply add more matches. You don't even need a default match, but it's probably convenient to use default to go to state A in this case.

always @(negedge Resetn, posedge Clock)
    if (Resetn == 0) //something :/
    else //something else :/

Something and something else would be register updates, such as {y2,y1} <= {Y2,Y1};. It is the clock edge sensitivity that turns the regs into flipflops.

Finally, since you should now understand what defines a reg width, why don't you make two bit wide regs named state and next_state to replace {y2,y1} and {Y2,Y1} respectively?

\$\endgroup\$
  • \$\begingroup\$ Found out since that sensitivity lists can be comma separated. I wonder why it's both. \$\endgroup\$ – Yann Vernier Jul 9 '13 at 19:13
1
\$\begingroup\$

Your state diagram looks good.

Your state transition table looks fine.

Your Verilog is not at all right. It's so far from right, it's hard to know where to begin fixing it.

In my experience, the best way to write Verilog, especially for synthesis, is to simply follow templates given by the synthesis tool vendor. For example, Xilinx has a Synthesis and Simulation Guide that shows how to code various kinds of structures in Verilog. The finite state machine examples start on p. 79.

Here's their example of a simple finite state machine in Verilog:

module v_fsm_1 (clk, reset, x1, outp);
 input clk, reset, x1;
 output outp;
 reg outp;
 reg [1:0] state;
 parameter s1 = 2'b00; parameter s2 = 2'b01;
 parameter s3 = 2'b10; parameter s4 = 2'b11;
 initial begin
   state = 2'b00;
 end

always@(posedge clk or posedge reset) begin
   if (reset) begin
     state <= s1; outp <= 1'b1;
   end
   else begin
     case (state)
       s1: begin
         if (x1==1'b1) begin
           state <= s2;
           outp <= 1'b1;
         end
         else begin
           state <= s3;
           outp <= 1'b0;
         end
       end
       s2: begin
         state <= s4; outp <= 1'b1;
       end
       s3: begin
         state <= s4; outp <= 1'b0;
       end
       s4: begin
         state <= s1; outp <= 1'b0;
       end
     endcase
   end
 end
endmodule

This is for a totally different state machine than yours, so you'll have to work out how to express your machine in this format.

Notice the structure: One giant case statement that handles all the state transitions and outputs. Also, they parameterize the state encoding so that the synthesis tool can reassign the actual codes if there's a reason to. For your assignment, since you had to determine the state encoding yourself, it's equally valid to just use literal values like 1'b00 in your code instead of parameter names like st0.

Another thing to notice is that Xilinx's style requires the output assignments "look ahead" to what the output needs to be in the next state. This does allow the output to depend on both the current state and the prior state, but this is a feature you don't need. For your problem it might be more straightforward to output generation into a separate block.

\$\endgroup\$
  • \$\begingroup\$ thanks I'll check it out. My book is downright awful at explaining stuff. \$\endgroup\$ – ModdedLife Apr 17 '13 at 3:25
  • \$\begingroup\$ Man this is confusing. This seems like nonsense. So would parameter be like my A,B,C,D? \$\endgroup\$ – ModdedLife Apr 17 '13 at 3:35
  • \$\begingroup\$ Yes, but notice you don't need to declare the width of a parameter. \$\endgroup\$ – The Photon Apr 17 '13 at 3:53
  • \$\begingroup\$ It's not necessary to declare states with parameter, the tools can extract and relabel state machines with in-line values. If this is done to assist the designer, then Verilog 2001's localparam is a better choice. \$\endgroup\$ – shuckc Apr 19 '13 at 9:01
  • \$\begingroup\$ @shuckc, not all tools are equal. I'd recommend OP should stick to the documented recommended style of his tool --- my answer is based on Xilinx's recommendation, but OP hasn't said what tool he is using, so those details may not apply. And in any case, it appears to be part of OP's homework to manually choose the states --- what the synthesis does with it is not really part of what's being asked about. \$\endgroup\$ – The Photon Apr 19 '13 at 15:29
0
\$\begingroup\$

Have a look at this. Might give you a better idea. This is a similar one but with a different input sequence Sequence_Detector

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.