I'm still pretty new to Verilog and all and could use some help completing/fixing my code for this problem. I have made the state diagram, state table/assignment, minimized the equation, and even have some of the Verilog done, but I'm just not too good at understanding Verilog.
Here's the prompt:
Derive a sequential circuit with one input (w) and one output (z) using D flip flops that detects an input sequence of 101. Use a Moore model, and show all of your work including the state machine, state table, state assignment, state assignment table, and the final circuit.
PS, I also don't know how to fully draw the circuit. But other than that, here's the progress I've made:
(I don't have a high enough rep to embed images if someone can do that for me, thanks)
State Table, Assignment, and Minimal equation
Besides the circuit diagram, I have the first part done. Now I have to implement this as a Verilog program.. even though I'm not quite sure where I'm going with it. I've looked at some examples and this is what I've got so far:
Verilog code so far
module my_circ(Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [3:1] y2, y1, Y2, Y1 //not sure about this line.. probably throws the rest off parameter [3:1] A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11; always @(w,y2,y1) case (y2) A: if (w) Y2 = 0; Y1 = 1; else Y2 = 0; Y1 = 0; B: if (w) Y2 = 0; Y1 = 1; /////////// I don't think this is right at all :( default: Y1 = ... always @(negedge Resetn, posedge Clock) if (Resetn == 0) //something :/ else //something else :/ assign z = (...); //something :/ endmodule
After trying to write that Verilog, I realize I'm just about clueless when it comes to implementing this :( I tried following different examples but all of the ones I can find use 3 states instead of 4 like this one. I think I should have multiple cases? And ugh idk where to set which variables and what to set them to.
Any advice will help me. Thanks.