1
\$\begingroup\$

I am learning about PCB stackup from this video.

It describes a 10-layer stackup as shown below. Layer 5 and layer 6 are power planes.

The author says to prevent power planes referencing each other, the dielectric thickness between layer 5 and 6 should be increased. My questions are:

  1. What will happen if power planes reference each other?

  2. What is meant by power planes referencing each other? Does it mean that the return current of one power plane will flow through the other power plane? If it does, what is the issue?

enter image description here

\$\endgroup\$

2 Answers 2

1
\$\begingroup\$

I presume you're referring to around 1hr 1min in the video. You seem to have more or less understood the issue with point 2.
Yes, it's an EMC consideration, the main point that your diagram doesn't convey, because it's not to scale, is the prepreg is much thinner than the core, and hence the coupling between layers separated by prepreg is much better than those separated by core.
When I say coupling, I mean capacitive, as any two conductors separated by a dielectric form a capacitor - in this case two PCB layers separated by either prepreg or core.

When designing PCBs, the path the current takes is important in both ways. It's not enough to think of the connection to the Ground net or plane as the end, all current must make its way back to the point of generation, through either ground planes, traces, wires or whatever. Any signals created by cross talk, interference or similar might not have GND as their point of generation either.

Let's say 100MHz is induced on a power line. If the coupling to another power layer is much stronger because those two layers are separated only by prepreg, then the return path for this signal could well be on this power layer rather than the ground. Remember that for AC, the DC values of different power rails doesn't matter, what matters is the impedance they present. In this way there's no reason why our 100MHz signal can't use another power plane as its return path.

When this happens that 100MHz signal is now also present on the other rail, and can cause EMC issues, or it could couple into devices using that rail. When our signal is now referenced between the power planes, our usual suppression techniques no longer work. For instance, we decouple our power supplies, but we decouple to ground. For 100MHz referenced from one plane to another, this decoupling doesn't do anything because the signal isn't trying to travel to the ground at all. EMI also doesn't care where a signal is referenced to or from, so this 100MHz bouncing around could easily be causing EMI problems.

\$\endgroup\$
0
\$\begingroup\$

A better term would be coupling, and cross capacitance. I would think this would be a non issue for most designs, but it's not negligible.

The best thing is it can be estimated (PCB area) and calculated (capacitance).

For a 1in sq parallel plate capacitor with 30mil spacing, the capacitance would be ~30pF with 6mil spacing it would be about 160pF.

Then ask yourself if putting one of those capacitors in between power planes would be an issue for RF. A better thing would be to put proper bypass capacitors and short the high frequency currents to the ground plane and let them return back to the source, with higher frequency currents this can be an issue.

So it really depends on how many square inches of copper you have between planes, estimate the capacitance and then see if it's a problem.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.