I'm testing the open loop transfer function of an op-amp circuit by following this schematic:


This is my LTspice schematic (keep in mind the actual op-amp circuit itself has been thoroughly checked, but if you think there might be a problem feel free to point it out):

LTspice schematic 1

Finally, this is the Bode plot I obtain (this was run on a new installation of LTSspice and no control panel settings were changed):

Bode plot 1

As you can see there is a single corner frequency and the gain crossover is not reached before 100 MHz. However, I believe that the correct Bode plot should present twk corner frequencies, and should drop to 0 dB before 100 MHz. It should look something like this (this was run on a different computer):

Sim and Bode plot 2

The simulated circuits are identical (except for the wire connecting T10 collector and T9 emitter, which does not produce the second corner frequency), but somehow the plots are different.

UPDATE: I have gone into the standard LTspice library and updated the transistors' capacitances values CJC (Cob) and CJE (Cib) as per the components' datasheets

.model 2N2222 NPN(IS=1E-14 VAF=100
+   BF=200 IKF=0.3 XTB=1.5 BR=3
+   CJC=8E-12 CJE=30E-12 TR=100E-9 TF=400E-12
+   ITF=1 VTF=2 XTF=3 RB=10 RC=.3 RE=.2 Vceo=30 Icrating=800m  mfg=NXP)

.model 2N2907 PNP(IS=1E-14 VAF=120
+   BF=250 IKF=0.3 XTB=1.5 BR=3
+   CJC=8E-12 CJE=30E-12 TR=100E-9 TF=400E-12
+   ITF=1 VTF=2 XTF=3 RB=10 RC=.3 RE=.2 Vceo=40 Icrating=600m mfg=NXP)

2N2222 transistor datasheet 2N2907 transistor datasheet

This made no difference to the original simulation and Bode plot. Maybe somebody with a keener eye can notice inconsistencies in the models.

If anybody has any idea as to why this is happening, I would be very glad with your help.

  • \$\begingroup\$ There has to be circuit differences or, something is different in your LTspice setup between the two computers. \$\endgroup\$
    – Andy aka
    Mar 18 at 12:33
  • \$\begingroup\$ Maybe there was a capacitor between T10's collector and base for the working version that somehow got removed in error. That's the normal place that internal compensation is placed. \$\endgroup\$
    – Andy aka
    Mar 18 at 12:44
  • \$\begingroup\$ The capacitor between T10's collector and base is added later as you say. This circuit is explicitly designed to test without compensation. I edited my original post and add the two circuits next to each other, what kind of settings could change the Bode plot so drastically? \$\endgroup\$
    – lostduck
    Mar 18 at 12:59
  • \$\begingroup\$ I'm sorry but despite what you say, there is likely a capacitor in the place I mention when you produced the 2nd AC plot. \$\endgroup\$
    – Andy aka
    Mar 18 at 13:08
  • \$\begingroup\$ You are speaking about "open-loop" - however, the last diagram shows an RC-feedback resulting in a differentiating block which is close to instability (but this is another point). \$\endgroup\$
    – LvW
    Mar 18 at 13:11

1 Answer 1


If anybody has any idea as to why this is happening, I would be very glad for your help.

No matter what you say and how similar the two schematics appear to be, you have a capacitor somewhere (possibly within a modified model) that is introducing a pole at around 1 kHz: -

enter image description here

At a phase shift of 45° there is a signal attenuation of 3 dB (1 kHz).

The response is so clear in that respect. Just dig a little deeper and you'll find it.

  • \$\begingroup\$ @Andyaka thank you for your answer! I understand what I'm looking for now. I assume the capacitance is due to the transistors' physics, is it possible that LTSpice does not account for this and can I enable it anywhere? \$\endgroup\$
    – lostduck
    Mar 18 at 15:51
  • \$\begingroup\$ Your transistors are much older than simulator programs then maybe they do not have their capacitance listed in their models. Wiring capacitance also must be added. \$\endgroup\$
    – Audioguru
    Mar 18 at 16:14
  • \$\begingroup\$ @lostduck you need to open the model of the transistors. I'm not sure how you do that in LTspice. \$\endgroup\$
    – Andy aka
    Mar 18 at 16:42
  • \$\begingroup\$ @Andyaka I have added my transistor model exploration to the original question. Unfortunately it hasn't changed anything \$\endgroup\$
    – lostduck
    Mar 18 at 17:51
  • \$\begingroup\$ Why has one of the circuits suddenly changed? The connection from T9 to T10 wasn't on the earlier versions of your question @lostduck also, you need to be comparing the circuit that works pspice models with the circuit that has a different AC characteristic. Nevertheless, there is extra capacitance somewhere that you haven't uncovered. \$\endgroup\$
    – Andy aka
    Mar 18 at 18:18

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